Misc: Use a 128b cache line size on Apple Silicon

Turns out it's not 64 bytes like I assumed. The things you learn.
2024-04-18 20:38:01 +10:00
parent fd21dd9729
commit 17b9736899
2 changed files with 9 additions and 2 deletions
--- a/src/core/gpu_backend.h
+++ b/src/core/gpu_backend.h
@ -83,8 +83,8 @@ protected:
  };

  FixedHeapArray<u8, COMMAND_QUEUE_SIZE> m_command_fifo_data;
-  alignas(64) std::atomic<u32> m_command_fifo_read_ptr{0};
-  alignas(64) std::atomic<u32> m_command_fifo_write_ptr{0};
+  alignas(HOST_CACHE_LINE_SIZE) std::atomic<u32> m_command_fifo_read_ptr{0};
+  alignas(HOST_CACHE_LINE_SIZE) std::atomic<u32> m_command_fifo_write_ptr{0};
 };

 #ifdef _MSC_VER