Add interrupt controller emulation

src/pse/cpu_core.h

@@ -28,14 +28,11 @@ public:
 
   TickCount Execute();
 
-  void SetSliceTicks(TickCount downcount)
-  {
-    m_slice_ticks = (downcount < m_slice_ticks ? downcount : m_slice_ticks);
-  }
-
   const Registers& GetRegs() const { return m_regs; }
   Registers& GetRegs() { return m_regs; }
 
+  void SetSliceTicks(TickCount downcount) { m_slice_ticks = (downcount < m_slice_ticks ? downcount : m_slice_ticks); }
+
   // Sets the PC and flushes the pipeline.
   void SetPC(u32 new_pc);
 
@@ -46,6 +43,10 @@ public:
   bool SafeWriteMemoryHalfWord(VirtualMemoryAddress addr, u16 value);
   bool SafeWriteMemoryWord(VirtualMemoryAddress addr, u32 value);
 
+  // External IRQs
+  void SetExternalInterrupt(u8 bit);
+  void ClearExternalInterrupt(u8 bit);
+
 private:
   template<MemoryAccessType type, MemoryAccessSize size, bool is_instruction_fetch, bool raise_exceptions>
   bool DoMemoryAccess(VirtualMemoryAddress address, u32& value);
@@ -78,6 +79,7 @@ private:
   // exceptions
   u32 GetExceptionVector(Exception excode) const;
   void RaiseException(Exception excode, u8 coprocessor = 0);
+  bool DispatchInterrupts();
 
   // flushes any load delays if present
   void FlushLoadDelay();
@@ -101,9 +103,8 @@ private:
   TickCount m_slice_ticks = 0;
 
   Registers m_regs = {};
+  Cop0Registers m_cop0_regs = {};
   Instruction m_next_instruction = {};
-  bool m_in_branch_delay_slot = false;
-  bool m_branched = false;
 
   // address of the instruction currently being executed
   u32 m_current_instruction_pc = 0;
@@ -113,11 +114,11 @@ private:
   u32 m_load_delay_old_value = 0;
   Reg m_next_load_delay_reg = Reg::count;
   u32 m_next_load_delay_old_value = 0;
+  bool m_in_branch_delay_slot = false;
+  bool m_branched = false;
 
   u32 m_cache_control = 0;
 
-  Cop0Registers m_cop0_regs = {};
-
   // data cache (used as scratchpad)
   std::array<u8, DCACHE_SIZE> m_dcache = {};
 };