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@ -2730,26 +2730,28 @@ bool CodeGenerator::Compile_cop0(Instruction instruction, const CodeCache::Instr
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// Emit an interrupt check on load of CAUSE/SR.
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Value sr_value = m_register_cache.AllocateScratch(RegSize_32);
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Value cause_value = m_register_cache.AllocateScratch(RegSize_32);
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m_register_cache.InhibitAllocation();
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// m_cop0_regs.sr.IEc && ((m_cop0_regs.cause.Ip & m_cop0_regs.sr.Im) != 0)
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LabelType no_interrupt;
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EmitLoadCPUStructField(sr_value.host_reg, sr_value.size, offsetof(State, cop0_regs.sr.bits));
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EmitLoadCPUStructField(cause_value.host_reg, cause_value.size, offsetof(State, cop0_regs.cause.bits));
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EmitBranchIfBitClear(sr_value.host_reg, sr_value.size, 0, &no_interrupt);
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m_register_cache.InhibitAllocation();
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EmitAnd(sr_value.host_reg, sr_value.host_reg, cause_value);
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EmitTest(sr_value.host_reg, Value::FromConstantU32(0xFF00));
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EmitConditionalBranch(Condition::Zero, false, &no_interrupt);
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m_register_cache.UninhibitAllocation();
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EmitBranch(GetCurrentFarCodePointer());
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SwitchToFarCode();
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m_register_cache.PushState();
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WriteNewPC(CalculatePC(), false);
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EmitStoreCPUStructField(offsetof(State, downcount), Value::FromConstantU32(0));
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EmitExceptionExit();
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m_register_cache.PopState();
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SwitchToNearCode();
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EmitBindLabel(&no_interrupt);
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m_register_cache.UninhibitAllocation();
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}
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else if (reg == Cop0Reg::DCIC && g_settings.cpu_recompiler_memory_exceptions)
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{
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@ -2780,8 +2782,10 @@ bool CodeGenerator::Compile_cop0(Instruction instruction, const CodeCache::Instr
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// exit block early if enabled
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EmitBranch(GetCurrentFarCodePointer());
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SwitchToFarCode();
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m_register_cache.PushState();
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WriteNewPC(CalculatePC(), false);
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EmitExceptionExit();
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m_register_cache.PopState();
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SwitchToNearCode();
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EmitBindLabel(¬_enabled);
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