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CPU/NewRec: Handle mtc0 rt, sr

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This commit is contained in:
Stenzek
2023-11-09 02:10:39 +10:00
parent 0ba50243ec
commit 312790c9a6
11 changed files with 163 additions and 55 deletions
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46
src/core/cpu_newrec_compiler_riscv64.cpp
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@ -586,14 +586,14 @@ void CPU::NewRec::RISCV64Compiler::EndBlock(const std::optional<u32>& newpc, boo
// flush regs
Flush(FLUSH_END_BLOCK);
EndAndLinkBlock(newpc, do_event_test);
EndAndLinkBlock(newpc, do_event_test, false);
}
void CPU::NewRec::RISCV64Compiler::EndBlockWithException(Exception excode)
{
// flush regs, but not pc, it's going to get overwritten
// flush cycles because of the GTE instruction stuff...
Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION);
Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
// TODO: flush load delay
// TODO: break for pcdrv
@ -604,14 +604,16 @@ void CPU::NewRec::RISCV64Compiler::EndBlockWithException(Exception excode)
EmitCall(reinterpret_cast<const void*>(static_cast<void (*)(u32, u32)>(&CPU::RaiseException)));
m_dirty_pc = false;
EndAndLinkBlock(std::nullopt, true);
EndAndLinkBlock(std::nullopt, true, false);
}
void CPU::NewRec::RISCV64Compiler::EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test)
void CPU::NewRec::RISCV64Compiler::EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test,
bool force_run_events)
{
// event test
// pc should've been flushed
DebugAssert(!m_dirty_pc);
DebugAssert(!m_dirty_pc && !m_block_ended);
m_block_ended = true;
// TODO: try extracting this to a function
// TODO: move the cycle flush in here..
@ -646,7 +648,11 @@ void CPU::NewRec::RISCV64Compiler::EndAndLinkBlock(const std::optional<u32>& new
}
// jump to dispatcher or next block
if (!newpc.has_value())
if (force_run_events)
{
rvEmitJmp(rvAsm, CodeCache::g_run_events_and_dispatch);
}
else if (!newpc.has_value())
{
rvEmitJmp(rvAsm, CodeCache::g_dispatcher);
}
@ -664,8 +670,6 @@ void CPU::NewRec::RISCV64Compiler::EndAndLinkBlock(const std::optional<u32>& new
rvEmitJmp(rvAsm, target);
}
}
m_block_ended = true;
}
const void* CPU::NewRec::RISCV64Compiler::EndCompile(u32* code_size, u32* far_code_size)
@ -2209,9 +2213,29 @@ void CPU::NewRec::RISCV64Compiler::TestInterrupts(const biscuit::GPR& sr)
rvAsm->ANDI(sr, sr, 0xFF);
SwitchToFarCode(true, &Assembler::BEQ, sr, zero);
BackupHostState();
Flush(FLUSH_FLUSH_MIPS_REGISTERS | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
EmitCall(reinterpret_cast<const void*>(&DispatchInterrupt));
EndBlock(std::nullopt, true);
Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
// Can't use EndBlockWithException() here, because it'll use the wrong PC.
// Can't use RaiseException() on the fast path if we're the last instruction, because the next PC is unknown.
if (!iinfo->is_last_instruction)
{
EmitMov(RARG1, Cop0Registers::CAUSE::MakeValueForException(Exception::INT, iinfo->is_branch_instruction, false,
(inst + 1)->cop.cop_n));
EmitMov(RARG2, m_compiler_pc);
EmitCall(reinterpret_cast<const void*>(static_cast<void (*)(u32, u32)>(&CPU::RaiseException)));
EndAndLinkBlock(std::nullopt, true, false);
}
else
{
if (m_dirty_pc)
EmitMov(RARG1, m_compiler_pc);
rvAsm->SW(biscuit::zero, PTR(&g_state.downcount));
if (m_dirty_pc)
rvAsm->SW(RARG1, PTR(&g_state.pc));
m_dirty_pc = false;
EndAndLinkBlock(std::nullopt, false, true);
}
RestoreHostState();
SwitchToNearCode(false);