SPU: Implement timing for RAM reads/writes

2020-03-29 01:12:37 +10:00
parent 20025b2ffd
commit 423f04325f
4 changed files with 260 additions and 88 deletions
--- a/src/core/dma.cpp
+++ b/src/core/dma.cpp
@ -206,15 +206,6 @@ TickCount DMA::GetTransferDelay(Channel channel) const
  const ChannelState& cs = m_state[static_cast<u32>(channel)];
  switch (channel)
  {
-    case Channel::SPU:
-    {
-      if (cs.channel_control.sync_mode == SyncMode::Request)
-        return (cs.block_control.request.GetBlockCount() * (cs.block_control.request.GetBlockSize() / 2));
-      else
-        return 1;
-    }
-    break;
-
    default:
      return 0;
  }