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Log: Simplify macros

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This commit is contained in:
Stenzek
2024-05-23 20:55:28 +10:00
parent 792717e03e
commit 4e922a34a7
144 changed files with 2273 additions and 2363 deletions
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119
src/core/cpu_newrec_compiler.cpp
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@ -71,7 +71,7 @@ void CPU::NewRec::Compiler::BeginBlock()
if (m_block->protection == CodeCache::PageProtectionMode::ManualCheck)
{
Log_DebugFmt("Generate manual protection for PC {:08X}", m_block->pc);
DEBUG_LOG("Generate manual protection for PC {:08X}", m_block->pc);
const u8* ram_ptr = Bus::g_ram + VirtualAddressToPhysical(m_block->pc);
const u8* shadow_ptr = reinterpret_cast<const u8*>(m_block->Instructions());
GenerateBlockProtectCheck(ram_ptr, shadow_ptr, m_block->size * sizeof(Instruction));
@ -103,7 +103,7 @@ const void* CPU::NewRec::Compiler::CompileBlock(CodeCache::Block* block, u32* ho
Reset(block, buffer.GetFreeCodePointer(), buffer.GetFreeCodeSpace(), buffer.GetFreeFarCodePointer(),
buffer.GetFreeFarCodeSpace());
Log_DebugFmt("Block range: {:08X} -> {:08X}", block->pc, block->pc + block->size * 4);
DEBUG_LOG("Block range: {:08X} -> {:08X}", block->pc, block->pc + block->size * 4);
BeginBlock();
@ -167,8 +167,8 @@ void CPU::NewRec::Compiler::SetConstantReg(Reg r, u32 v)
if (const std::optional<u32> hostreg = CheckHostReg(0, HR_TYPE_CPU_REG, r); hostreg.has_value())
{
Log_DebugFmt("Discarding guest register {} in host register {} due to constant set", GetRegName(r),
GetHostRegName(hostreg.value()));
DEBUG_LOG("Discarding guest register {} in host register {} due to constant set", GetRegName(r),
GetHostRegName(hostreg.value()));
FreeHostReg(hostreg.value());
}
}
@ -178,7 +178,7 @@ void CPU::NewRec::Compiler::CancelLoadDelaysToReg(Reg reg)
if (m_load_delay_register != reg)
return;
Log_DebugFmt("Cancelling load delay to {}", GetRegName(reg));
DEBUG_LOG("Cancelling load delay to {}", GetRegName(reg));
m_load_delay_register = Reg::count;
if (m_load_delay_value_register != NUM_HOST_REGS)
ClearHostReg(m_load_delay_value_register);
@ -196,7 +196,7 @@ void CPU::NewRec::Compiler::UpdateLoadDelay()
// thankfully since this only happens on the first instruction, we can get away with just killing anything which
// isn't in write mode, because nothing could've been written before it, and the new value overwrites any
// load-delayed value
Log_DebugPrint("Invalidating non-dirty registers, and flushing load delay from state");
DEBUG_LOG("Invalidating non-dirty registers, and flushing load delay from state");
constexpr u32 req_flags = (HR_ALLOCATED | HR_MODE_WRITE);
@ -206,7 +206,7 @@ void CPU::NewRec::Compiler::UpdateLoadDelay()
if (ra.type != HR_TYPE_CPU_REG || !IsHostRegAllocated(i) || ((ra.flags & req_flags) == req_flags))
continue;
Log_DebugFmt("Freeing non-dirty cached register {} in {}", GetRegName(ra.reg), GetHostRegName(i));
DEBUG_LOG("Freeing non-dirty cached register {} in {}", GetRegName(ra.reg), GetHostRegName(i));
DebugAssert(!(ra.flags & HR_MODE_WRITE));
ClearHostReg(i);
}
@ -217,7 +217,7 @@ void CPU::NewRec::Compiler::UpdateLoadDelay()
if (!HasConstantReg(static_cast<Reg>(i)) || HasDirtyConstantReg(static_cast<Reg>(i)))
continue;
Log_DebugFmt("Clearing non-dirty constant {}", GetRegName(static_cast<Reg>(i)));
DEBUG_LOG("Clearing non-dirty constant {}", GetRegName(static_cast<Reg>(i)));
ClearConstantReg(static_cast<Reg>(i));
}
@ -264,8 +264,8 @@ void CPU::NewRec::Compiler::FinishLoadDelay()
// kill any (old) cached value for this register
DeleteMIPSReg(m_load_delay_register, false);
Log_DebugFmt("Finished delayed load to {} in host register {}", GetRegName(m_load_delay_register),
GetHostRegName(m_load_delay_value_register));
DEBUG_LOG("Finished delayed load to {} in host register {}", GetRegName(m_load_delay_register),
GetHostRegName(m_load_delay_value_register));
// and swap the mode over so it gets written back later
HostRegAlloc& ra = m_host_regs[m_load_delay_value_register];
@ -275,7 +275,7 @@ void CPU::NewRec::Compiler::FinishLoadDelay()
ra.type = HR_TYPE_CPU_REG;
// constants are gone
Log_DebugFmt("Clearing constant in {} due to load delay", GetRegName(m_load_delay_register));
DEBUG_LOG("Clearing constant in {} due to load delay", GetRegName(m_load_delay_register));
ClearConstantReg(m_load_delay_register);
m_load_delay_register = Reg::count;
@ -490,7 +490,7 @@ bool CPU::NewRec::Compiler::TrySwapDelaySlot(Reg rs, Reg rt, Reg rd)
is_safe:
#ifdef _DEBUG
Log_DebugFmt("Swapping delay slot {:08X} {}", m_current_instruction_pc + 4, disasm);
DEBUG_LOG("Swapping delay slot {:08X} {}", m_current_instruction_pc + 4, disasm);
#endif
CompileBranchDelaySlot();
@ -502,7 +502,7 @@ is_safe:
is_unsafe:
#ifdef _DEBUG
Log_DebugFmt("NOT swapping delay slot {:08X} {}", m_current_instruction_pc + 4, disasm);
DEBUG_LOG("NOT swapping delay slot {:08X} {}", m_current_instruction_pc + 4, disasm);
#endif
return false;
@ -598,8 +598,8 @@ u32 CPU::NewRec::Compiler::GetFreeHostReg(u32 flags)
if (caller_saved_lowest_count < lowest_count)
{
Log_DebugFmt("Moving caller-saved host register {} with MIPS register {} to {} for allocation",
GetHostRegName(lowest), GetRegName(ra.reg), GetHostRegName(caller_saved_lowest));
DEBUG_LOG("Moving caller-saved host register {} with MIPS register {} to {} for allocation",
GetHostRegName(lowest), GetRegName(ra.reg), GetHostRegName(caller_saved_lowest));
if (IsHostRegAllocated(caller_saved_lowest))
FreeHostReg(caller_saved_lowest);
CopyHostReg(caller_saved_lowest, lowest);
@ -609,20 +609,19 @@ u32 CPU::NewRec::Compiler::GetFreeHostReg(u32 flags)
}
}
Log_DebugFmt("Freeing register {} in host register {} for allocation", GetRegName(ra.reg),
GetHostRegName(lowest));
DEBUG_LOG("Freeing register {} in host register {} for allocation", GetRegName(ra.reg), GetHostRegName(lowest));
}
break;
case HR_TYPE_LOAD_DELAY_VALUE:
{
Log_DebugFmt("Freeing load delay register {} in host register {} for allocation", GetHostRegName(lowest),
GetRegName(ra.reg));
DEBUG_LOG("Freeing load delay register {} in host register {} for allocation", GetHostRegName(lowest),
GetRegName(ra.reg));
}
break;
case HR_TYPE_NEXT_LOAD_DELAY_VALUE:
{
Log_DebugFmt("Freeing next load delay register {} in host register {} due for allocation", GetRegName(ra.reg),
GetHostRegName(lowest));
DEBUG_LOG("Freeing next load delay register {} in host register {} due for allocation", GetRegName(ra.reg),
GetHostRegName(lowest));
}
break;
default:
@ -680,8 +679,8 @@ u32 CPU::NewRec::Compiler::AllocateHostReg(u32 flags, HostRegAllocType type /* =
{
DebugAssert(reg != Reg::zero);
Log_DebugFmt("Allocate host reg {} to guest reg {} in {} mode", GetHostRegName(hreg), GetRegName(reg),
GetReadWriteModeString(flags));
DEBUG_LOG("Allocate host reg {} to guest reg {} in {} mode", GetHostRegName(hreg), GetRegName(reg),
GetReadWriteModeString(flags));
if (flags & HR_MODE_READ)
{
@ -690,7 +689,7 @@ u32 CPU::NewRec::Compiler::AllocateHostReg(u32 flags, HostRegAllocType type /* =
if (HasConstantReg(reg))
{
// may as well flush it now
Log_DebugFmt("Flush constant register in guest reg {} to host reg {}", GetRegName(reg), GetHostRegName(hreg));
DEBUG_LOG("Flush constant register in guest reg {} to host reg {}", GetRegName(reg), GetHostRegName(hreg));
LoadHostRegWithConstant(hreg, GetConstantRegU32(reg));
m_constant_regs_dirty.reset(static_cast<u8>(reg));
ra.flags |= HR_MODE_WRITE;
@ -704,8 +703,8 @@ u32 CPU::NewRec::Compiler::AllocateHostReg(u32 flags, HostRegAllocType type /* =
if (flags & HR_MODE_WRITE && HasConstantReg(reg))
{
DebugAssert(reg != Reg::zero);
Log_DebugFmt("Clearing constant register in guest reg {} due to write mode in {}", GetRegName(reg),
GetHostRegName(hreg));
DEBUG_LOG("Clearing constant register in guest reg {} due to write mode in {}", GetRegName(reg),
GetHostRegName(hreg));
ClearConstantReg(reg);
}
@ -715,8 +714,8 @@ u32 CPU::NewRec::Compiler::AllocateHostReg(u32 flags, HostRegAllocType type /* =
case HR_TYPE_LOAD_DELAY_VALUE:
{
DebugAssert(!m_load_delay_dirty && (!HasLoadDelay() || !(flags & HR_MODE_WRITE)));
Log_DebugFmt("Allocating load delayed guest register {} in host reg {} in {} mode", GetRegName(reg),
GetHostRegName(hreg), GetReadWriteModeString(flags));
DEBUG_LOG("Allocating load delayed guest register {} in host reg {} in {} mode", GetRegName(reg),
GetHostRegName(hreg), GetReadWriteModeString(flags));
m_load_delay_register = reg;
m_load_delay_value_register = hreg;
if (flags & HR_MODE_READ)
@ -726,8 +725,8 @@ u32 CPU::NewRec::Compiler::AllocateHostReg(u32 flags, HostRegAllocType type /* =
case HR_TYPE_NEXT_LOAD_DELAY_VALUE:
{
Log_DebugFmt("Allocating next load delayed guest register {} in host reg {} in {} mode", GetRegName(reg),
GetHostRegName(hreg), GetReadWriteModeString(flags));
DEBUG_LOG("Allocating next load delayed guest register {} in host reg {} in {} mode", GetRegName(reg),
GetHostRegName(hreg), GetReadWriteModeString(flags));
m_next_load_delay_register = reg;
m_next_load_delay_value_register = hreg;
if (flags & HR_MODE_READ)
@ -738,7 +737,7 @@ u32 CPU::NewRec::Compiler::AllocateHostReg(u32 flags, HostRegAllocType type /* =
case HR_TYPE_TEMP:
{
DebugAssert(!(flags & (HR_MODE_READ | HR_MODE_WRITE)));
Log_DebugFmt("Allocate host reg {} as temporary", GetHostRegName(hreg));
DEBUG_LOG("Allocate host reg {} as temporary", GetHostRegName(hreg));
}
break;
@ -764,13 +763,13 @@ std::optional<u32> CPU::NewRec::Compiler::CheckHostReg(u32 flags, HostRegAllocTy
{
DebugAssert(type == HR_TYPE_CPU_REG);
if (!(ra.flags & HR_MODE_WRITE))
Log_DebugFmt("Switch guest reg {} from read to read-write in host reg {}", GetRegName(reg), GetHostRegName(i));
DEBUG_LOG("Switch guest reg {} from read to read-write in host reg {}", GetRegName(reg), GetHostRegName(i));
if (HasConstantReg(reg))
{
DebugAssert(reg != Reg::zero);
Log_DebugFmt("Clearing constant register in guest reg {} due to write mode in {}", GetRegName(reg),
GetHostRegName(i));
DEBUG_LOG("Clearing constant register in guest reg {} due to write mode in {}", GetRegName(reg),
GetHostRegName(i));
ClearConstantReg(reg);
}
@ -784,7 +783,7 @@ std::optional<u32> CPU::NewRec::Compiler::CheckHostReg(u32 flags, HostRegAllocTy
{
// Need to move it to one which is
const u32 new_reg = GetFreeHostReg(HR_CALLEE_SAVED);
Log_DebugFmt("Rename host reg {} to {} for callee saved", GetHostRegName(i), GetHostRegName(new_reg));
DEBUG_LOG("Rename host reg {} to {} for callee saved", GetHostRegName(i), GetHostRegName(new_reg));
CopyHostReg(new_reg, i);
SwapHostRegAlloc(i, new_reg);
@ -826,7 +825,7 @@ void CPU::NewRec::Compiler::FlushHostReg(u32 reg)
case HR_TYPE_CPU_REG:
{
DebugAssert(ra.reg > Reg::zero && ra.reg < Reg::count);
Log_DebugFmt("Flushing register {} in host register {} to state", GetRegName(ra.reg), GetHostRegName(reg));
DEBUG_LOG("Flushing register {} in host register {} to state", GetRegName(ra.reg), GetHostRegName(reg));
StoreHostRegToCPUPointer(reg, &g_state.regs.r[static_cast<u8>(ra.reg)]);
}
break;
@ -834,8 +833,8 @@ void CPU::NewRec::Compiler::FlushHostReg(u32 reg)
case HR_TYPE_LOAD_DELAY_VALUE:
{
DebugAssert(m_load_delay_value_register == reg);
Log_DebugFmt("Flushing load delayed register {} in host register {} to state", GetRegName(ra.reg),
GetHostRegName(reg));
DEBUG_LOG("Flushing load delayed register {} in host register {} to state", GetRegName(ra.reg),
GetHostRegName(reg));
StoreHostRegToCPUPointer(reg, &g_state.load_delay_value);
m_load_delay_value_register = NUM_HOST_REGS;
@ -845,8 +844,8 @@ void CPU::NewRec::Compiler::FlushHostReg(u32 reg)
case HR_TYPE_NEXT_LOAD_DELAY_VALUE:
{
DebugAssert(m_next_load_delay_value_register == reg);
Log_WarningFmt("Flushing NEXT load delayed register {} in host register {} to state", GetRegName(ra.reg),
GetHostRegName(reg));
WARNING_LOG("Flushing NEXT load delayed register {} in host register {} to state", GetRegName(ra.reg),
GetHostRegName(reg));
StoreHostRegToCPUPointer(reg, &g_state.next_load_delay_value);
m_next_load_delay_value_register = NUM_HOST_REGS;
@ -864,7 +863,7 @@ void CPU::NewRec::Compiler::FlushHostReg(u32 reg)
void CPU::NewRec::Compiler::FreeHostReg(u32 reg)
{
DebugAssert(IsHostRegAllocated(reg));
Log_DebugFmt("Freeing host register {}", GetHostRegName(reg));
DEBUG_LOG("Freeing host register {}", GetHostRegName(reg));
FlushHostReg(reg);
ClearHostReg(reg);
}
@ -906,18 +905,18 @@ void CPU::NewRec::Compiler::RenameHostReg(u32 reg, u32 new_flags, HostRegAllocTy
if (new_type == HR_TYPE_CPU_REG)
{
Log_DebugFmt("Renaming host reg {} to guest reg {}", GetHostRegName(reg), GetRegName(new_reg));
DEBUG_LOG("Renaming host reg {} to guest reg {}", GetHostRegName(reg), GetRegName(new_reg));
}
else if (new_type == HR_TYPE_NEXT_LOAD_DELAY_VALUE)
{
Log_DebugFmt("Renaming host reg {} to load delayed guest reg {}", GetHostRegName(reg), GetRegName(new_reg));
DEBUG_LOG("Renaming host reg {} to load delayed guest reg {}", GetHostRegName(reg), GetRegName(new_reg));
DebugAssert(m_next_load_delay_register == Reg::count && m_next_load_delay_value_register == NUM_HOST_REGS);
m_next_load_delay_register = new_reg;
m_next_load_delay_value_register = reg;
}
else
{
Log_DebugFmt("Renaming host reg {} to temp", GetHostRegName(reg));
DEBUG_LOG("Renaming host reg {} to temp", GetHostRegName(reg));
}
HostRegAlloc& ra = m_host_regs[reg];
@ -983,7 +982,7 @@ bool CPU::NewRec::Compiler::TryRenameMIPSReg(Reg to, Reg from, u32 fromhost, Reg
if (to == from || to == other || !iinfo->RenameTest(from))
return false;
Log_DebugFmt("Renaming MIPS register {} to {}", GetRegName(from), GetRegName(to));
DEBUG_LOG("Renaming MIPS register {} to {}", GetRegName(from), GetRegName(to));
if (iinfo->LiveTest(from))
FlushHostReg(fromhost);
@ -1090,8 +1089,8 @@ void CPU::NewRec::Compiler::Flush(u32 flags)
void CPU::NewRec::Compiler::FlushConstantReg(Reg r)
{
DebugAssert(m_constant_regs_valid.test(static_cast<u32>(r)));
Log_DebugFmt("Writing back register {} with constant value 0x{:08X}", GetRegName(r),
m_constant_reg_values[static_cast<u32>(r)]);
DEBUG_LOG("Writing back register {} with constant value 0x{:08X}", GetRegName(r),
m_constant_reg_values[static_cast<u32>(r)]);
StoreConstantToCPUPointer(m_constant_reg_values[static_cast<u32>(r)], &g_state.regs.r[static_cast<u32>(r)]);
m_constant_regs_dirty.reset(static_cast<u32>(r));
}
@ -1179,8 +1178,8 @@ void CPU::NewRec::Compiler::CompileInstruction()
#ifdef _DEBUG
TinyString str;
DisassembleInstruction(&str, m_current_instruction_pc, inst->bits);
Log_DebugFmt("Compiling{} {:08X}: {}", m_current_instruction_branch_delay_slot ? " branch delay slot" : "",
m_current_instruction_pc, str);
DEBUG_LOG("Compiling{} {:08X}: {}", m_current_instruction_branch_delay_slot ? " branch delay slot" : "",
m_current_instruction_pc, str);
#endif
m_cycles++;
@ -1390,7 +1389,7 @@ void CPU::NewRec::Compiler::CompileTemplate(void (Compiler::*const_func)(Compile
if (!(tflags & TF_NO_NOP) && (!g_settings.cpu_recompiler_memory_exceptions || !(tflags & TF_CAN_OVERFLOW)) &&
((tflags & TF_WRITES_T && rt == Reg::zero) || (tflags & TF_WRITES_D && rd == Reg::zero)))
{
Log_DebugPrint("Skipping instruction because it writes to zero");
DEBUG_LOG("Skipping instruction because it writes to zero");
return;
}
@ -1437,7 +1436,7 @@ void CPU::NewRec::Compiler::CompileTemplate(void (Compiler::*const_func)(Compile
if (tflags & TF_COMMUTATIVE && !(tflags & TF_WRITES_T) &&
((HasConstantReg(rs) && !HasConstantReg(rt)) || (tflags & TF_WRITES_D && rd == rt)))
{
Log_DebugFmt("Swapping S:{} and T:{} due to commutative op and constants", GetRegName(rs), GetRegName(rt));
DEBUG_LOG("Swapping S:{} and T:{} due to commutative op and constants", GetRegName(rs), GetRegName(rt));
std::swap(rs, rt);
}
@ -1638,7 +1637,7 @@ void CPU::NewRec::Compiler::CompileLoadStoreTemplate(void (Compiler::*func)(Comp
if (!Bus::CanUseFastmemForAddress(addr.value()))
{
Log_DebugFmt("Not using fastmem for {:08X}", addr.value());
DEBUG_LOG("Not using fastmem for {:08X}", addr.value());
use_fastmem = false;
}
}
@ -1647,7 +1646,7 @@ void CPU::NewRec::Compiler::CompileLoadStoreTemplate(void (Compiler::*func)(Comp
spec_addr = SpecExec_LoadStoreAddr();
if (use_fastmem && spec_addr.has_value() && !Bus::CanUseFastmemForAddress(spec_addr.value()))
{
Log_DebugFmt("Not using fastmem for speculative {:08X}", spec_addr.value());
DEBUG_LOG("Not using fastmem for speculative {:08X}", spec_addr.value());
use_fastmem = false;
}
@ -1707,9 +1706,9 @@ void CPU::NewRec::Compiler::CompileLoadStoreTemplate(void (Compiler::*func)(Comp
if (phys_spec_addr >= VirtualAddressToPhysical(m_block->pc) &&
phys_spec_addr < VirtualAddressToPhysical(m_block->pc + (m_block->size * sizeof(Instruction))))
{
Log_WarningFmt("Instruction {:08X} speculatively writes to {:08X} inside block {:08X}-{:08X}. Truncating block.",
m_current_instruction_pc, phys_spec_addr, m_block->pc,
m_block->pc + (m_block->size * sizeof(Instruction)));
WARNING_LOG("Instruction {:08X} speculatively writes to {:08X} inside block {:08X}-{:08X}. Truncating block.",
m_current_instruction_pc, phys_spec_addr, m_block->pc,
m_block->pc + (m_block->size * sizeof(Instruction)));
TruncateBlock();
}
}
@ -2198,7 +2197,7 @@ void CPU::NewRec::Compiler::Compile_mfc0(CompileFlags cf)
const u32* ptr = GetCop0RegPtr(r);
if (!ptr)
{
Log_ErrorFmt("Read from unknown cop0 reg {}", static_cast<u32>(r));
ERROR_LOG("Read from unknown cop0 reg {}", static_cast<u32>(r));
Compile_Fallback();
return;
}
@ -2304,7 +2303,7 @@ void CPU::NewRec::Compiler::AddGTETicks(TickCount ticks)
{
// TODO: check, int has +1 here
m_gte_done_cycle = m_cycles + ticks;
Log_DebugFmt("Adding {} GTE ticks", ticks);
DEBUG_LOG("Adding {} GTE ticks", ticks);
}
void CPU::NewRec::Compiler::StallUntilGTEComplete()
@ -2319,14 +2318,14 @@ void CPU::NewRec::Compiler::StallUntilGTEComplete()
// simple case - in block scheduling
if (m_gte_done_cycle > m_cycles)
{
Log_DebugFmt("Stalling for {} ticks from GTE", m_gte_done_cycle - m_cycles);
DEBUG_LOG("Stalling for {} ticks from GTE", m_gte_done_cycle - m_cycles);
m_cycles += (m_gte_done_cycle - m_cycles);
}
}
else
{
// switch to in block scheduling
Log_DebugPrint("Flushing GTE stall from state");
DEBUG_LOG("Flushing GTE stall from state");
Flush(FLUSH_GTE_STALL_FROM_STATE);
}