CPU/Interpreter: Load delay check should be a debug assertion
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@@ -362,7 +362,7 @@ ALWAYS_INLINE static void WriteReg(Reg rd, u32 value)
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ALWAYS_INLINE_RELEASE static void WriteRegDelayed(Reg rd, u32 value)
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ALWAYS_INLINE_RELEASE static void WriteRegDelayed(Reg rd, u32 value)
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{
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{
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Assert(g_state.next_load_delay_reg == Reg::count);
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DebugAssert(g_state.next_load_delay_reg == Reg::count);
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if (rd == Reg::zero)
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if (rd == Reg::zero)
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return;
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return;
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