Pad: Fix timing issues w/ BIOS
This commit is contained in:
119
src/pse/pad.cpp
119
src/pse/pad.cpp
@ -3,14 +3,16 @@
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#include "common/state_wrapper.h"
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#include "interrupt_controller.h"
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#include "pad_device.h"
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#include "system.h"
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Log_SetChannel(Pad);
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Pad::Pad() = default;
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Pad::~Pad() = default;
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bool Pad::Initialize(InterruptController* interrupt_controller)
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bool Pad::Initialize(System* system, InterruptController* interrupt_controller)
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{
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m_system = system;
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m_interrupt_controller = interrupt_controller;
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return true;
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}
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@ -22,6 +24,8 @@ void Pad::Reset()
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bool Pad::DoState(StateWrapper& sw)
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{
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sw.Do(&m_state);
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sw.Do(&m_ticks_remaining);
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sw.Do(&m_JOY_CTRL.bits);
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sw.Do(&m_JOY_STAT.bits);
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sw.Do(&m_JOY_MODE.bits);
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@ -49,7 +53,11 @@ u32 Pad::ReadRegister(u32 offset)
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}
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case 0x04: // JOY_STAT
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return m_JOY_STAT.bits;
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{
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const u32 bits = m_JOY_STAT.bits;
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m_JOY_STAT.ACKINPUT = false;
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return bits;
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}
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case 0x08: // JOY_MODE
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return ZeroExtend32(m_JOY_MODE.bits);
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@ -78,8 +86,8 @@ void Pad::WriteRegister(u32 offset, u32 value)
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m_TX_FIFO.Push(Truncate8(value));
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if (m_JOY_CTRL.SELECT)
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DoTransfer();
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if (!IsTransmitting() && CanTransfer())
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BeginTransfer();
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return;
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}
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@ -96,13 +104,19 @@ void Pad::WriteRegister(u32 offset, u32 value)
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if (m_JOY_CTRL.ACK)
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{
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// reset stat bits
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m_JOY_STAT.ACKINPUTLEVEL = false;
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m_JOY_STAT.INTR = false;
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m_JOY_CTRL.ACK = true;
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}
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if (!old_select && m_JOY_CTRL.SELECT && !m_TX_FIFO.IsEmpty())
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DoTransfer();
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if (!m_JOY_CTRL.SELECT || !m_JOY_CTRL.TXEN)
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{
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if (IsTransmitting())
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EndTransfer();
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}
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else
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{
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if (!IsTransmitting() && CanTransfer())
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BeginTransfer();
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}
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return;
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}
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@ -126,8 +140,28 @@ void Pad::WriteRegister(u32 offset, u32 value)
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}
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}
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void Pad::Execute(TickCount ticks)
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{
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switch (m_state)
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{
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case State::Idle:
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break;
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case State::Transmitting:
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{
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m_ticks_remaining -= ticks;
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if (m_ticks_remaining <= 0)
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DoTransfer();
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}
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break;
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}
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}
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void Pad::SoftReset()
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{
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if (IsTransmitting())
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EndTransfer();
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m_JOY_CTRL.bits = 0;
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m_JOY_STAT.bits = 0;
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m_JOY_MODE.bits = 0;
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@ -143,35 +177,84 @@ void Pad::UpdateJoyStat()
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m_JOY_STAT.TXRDY = !m_TX_FIFO.IsFull();
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}
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void Pad::BeginTransfer()
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{
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DebugAssert(m_state == State::Idle && CanTransfer());
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Log_DebugPrintf("Starting transfer");
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m_JOY_CTRL.RXEN = true;
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// The transfer or the interrupt must be delayed, otherwise the BIOS thinks there's no device detected.
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// It seems to do something resembling the following:
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// 1) Sets the control register up for transmitting, interrupt on ACK.
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// 2) Writes 0x01 to the TX FIFO.
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// 3) Delays for a bit.
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// 4) Writes ACK to the control register, clearing the interrupt flag.
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// 5) Clears IRQ7 in the interrupt controller.
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// 6) Waits until the RX FIFO is not empty, reads the first byte to $zero.
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// 7) Checks if the interrupt status register had IRQ7 set. If not, no device connected.
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//
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// Performing the transfer immediately will result in both the INTR bit and the bit in the interrupt
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// controller being discarded in (4)/(5), but this bit was set by the *new* transfer. Therefore, the
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// test in (7) will fail, and it won't send any more data. So, the transfer/interrupt must be delayed
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// until after (4) and (5) have been completed.
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m_system->Synchronize();
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m_state = State::Transmitting;
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m_ticks_remaining = TRANSFER_TICKS;
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m_system->SetDowncount(m_ticks_remaining);
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}
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void Pad::DoTransfer()
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{
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Log_DebugPrintf("Transferring slot %d", m_JOY_CTRL.SLOT.GetValue());
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const std::shared_ptr<PadDevice>& dev = m_devices[m_JOY_CTRL.SLOT];
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if (!dev)
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if (!dev || !CanTransfer())
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{
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// no device present, don't set ACK and read hi-z
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m_TX_FIFO.Clear();
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m_RX_FIFO.Clear();
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m_RX_FIFO.Push(0xFF);
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UpdateJoyStat();
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EndTransfer();
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return;
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}
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while (!m_TX_FIFO.IsEmpty())
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{
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const u8 data_out = m_TX_FIFO.Pop();
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u8 data_in;
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m_JOY_STAT.ACKINPUTLEVEL |= dev->Transfer(data_out, &data_in);
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m_RX_FIFO.Push(data_in);
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m_JOY_CTRL.RXEN = true;
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}
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// set rx?
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m_JOY_CTRL.RXEN = true;
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if (m_JOY_STAT.ACKINPUTLEVEL && m_JOY_CTRL.ACKINTEN)
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const u8 data_out = m_TX_FIFO.Pop();
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u8 data_in;
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m_JOY_STAT.ACKINPUT |= dev->Transfer(data_out, &data_in);
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m_RX_FIFO.Push(data_in);
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if (m_JOY_STAT.ACKINPUT && m_JOY_CTRL.ACKINTEN)
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{
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Log_DebugPrintf("Triggering interrupt");
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m_JOY_STAT.INTR = true;
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m_interrupt_controller->InterruptRequest(InterruptController::IRQ::IRQ7);
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}
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if (m_TX_FIFO.IsEmpty())
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{
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EndTransfer();
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}
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else
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{
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// queue the next byte
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m_ticks_remaining += TRANSFER_TICKS;
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m_system->SetDowncount(m_ticks_remaining);
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}
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UpdateJoyStat();
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}
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void Pad::EndTransfer()
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{
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DebugAssert(m_state == State::Transmitting);
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Log_DebugPrintf("Ending transfer");
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m_state = State::Idle;
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m_ticks_remaining = 0;
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}
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