Misc: Align CPU state and SPU voices to cache lines

Fixes the ~12% performance regression from the texture replacement
namespace'ify commit. Apparently LTO was placing the CPU struct in the
middle of a cache line...
This commit is contained in:
Stenzek
2024-07-06 18:49:35 +10:00
parent d021a61eb5
commit 77488db3dc
4 changed files with 4 additions and 3 deletions

View File

@ -89,7 +89,7 @@ static bool WriteMemoryByte(VirtualMemoryAddress addr, u32 value);
static bool WriteMemoryHalfWord(VirtualMemoryAddress addr, u32 value);
static bool WriteMemoryWord(VirtualMemoryAddress addr, u32 value);
State g_state;
alignas(HOST_CACHE_LINE_SIZE) State g_state;
bool TRACE_EXECUTION = false;
static fastjmp_buf s_jmp_buf;