Misc: Align CPU state and SPU voices to cache lines
Fixes the ~12% performance regression from the texture replacement namespace'ify commit. Apparently LTO was placing the CPU struct in the middle of a cache line...
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@ -89,7 +89,7 @@ static bool WriteMemoryByte(VirtualMemoryAddress addr, u32 value);
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static bool WriteMemoryHalfWord(VirtualMemoryAddress addr, u32 value);
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static bool WriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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State g_state;
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alignas(HOST_CACHE_LINE_SIZE) State g_state;
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bool TRACE_EXECUTION = false;
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static fastjmp_buf s_jmp_buf;
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