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DMA: Determine slice size based on whether pad is transmitting

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Plenty of games seem to suffer from this issue where they have
a linked list DMA going while polling the controller. Using a
too-large slice size will result in the serial timing being off,
and the game thinking the controller is disconnected. So we
don't hurt performance too much for the general case, we reduce
this to equal CPU and DMA time when the controller is
transferring, but otherwise leave it at the higher size.
This commit is contained in:
Connor McLaughlin
2021-01-06 00:00:56 +10:00
parent 98a4e59f52
commit 845cd37835
3 changed files with 39 additions and 8 deletions
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7
src/core/pad.h
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@ -31,6 +31,8 @@ public:
u32 ReadRegister(u32 offset);
void WriteRegister(u32 offset, u32 value);
ALWAYS_INLINE bool IsTransmitting() const { return m_state != State::Idle; }
private:
static constexpr u32 NUM_SLOTS = 2;
@ -87,10 +89,9 @@ private:
BitField<u16, u8, 8, 1> clk_polarity;
};
bool IsTransmitting() const { return m_state != State::Idle; }
bool CanTransfer() const { return m_transmit_buffer_full && m_JOY_CTRL.SELECT && m_JOY_CTRL.TXEN; }
ALWAYS_INLINE bool CanTransfer() const { return m_transmit_buffer_full && m_JOY_CTRL.SELECT && m_JOY_CTRL.TXEN; }
TickCount GetTransferTicks() const { return static_cast<TickCount>(ZeroExtend32(m_JOY_BAUD) * 8); }
ALWAYS_INLINE TickCount GetTransferTicks() const { return static_cast<TickCount>(ZeroExtend32(m_JOY_BAUD) * 8); }
// From @JaCzekanski
// ACK lasts ~96 ticks or approximately 2.84us at master clock (not implemented).