sgilissen/llamaplayer
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

GPU: Set idle bit during VRAM upload

Browse Source 
Tenga Seiha does a bunch of completely-invalid VRAM writes on boot, then
expects GPU idle to be set. It's unclear what actually happens, I need to
write another test, but for now, just skip these uploads. Not setting GPU
idle during the write command breaks Doom, so that's not an option.
This commit is contained in:
Stenzek
2024-06-13 18:29:12 +10:00
parent edea81d151
commit ac1bb905fe
2 changed files with 18 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
src/core/gpu.cpp
View File

@ -445,22 +445,7 @@ void GPU::UpdateDMARequest()
void GPU::UpdateGPUIdle()
{
switch (m_blitter_state)
{
case BlitterState::Idle:
case BlitterState::DrawingPolyLine:
m_GPUSTAT.gpu_idle = (m_pending_command_ticks <= 0 && m_fifo.IsEmpty());
break;
case BlitterState::WritingVRAM:
case BlitterState::ReadingVRAM:
m_GPUSTAT.gpu_idle = m_fifo.IsEmpty();
break;
default:
UnreachableCode();
break;
}
m_GPUSTAT.gpu_idle = (m_blitter_state == BlitterState::Idle && m_pending_command_ticks <= 0 && m_fifo.IsEmpty());
}
u32 GPU::ReadRegister(u32 offset)