sgilissen/llamaplayer
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

CPU/NewRec: Allocate callee-saved before flush in lwx/swx

Browse Source 
It might move a callee-saved -> caller-saved reg, in which case it's
going to get clobbered when the loadstore function is called.

SaGa Frontier 2 with PGXP on x64.
This commit is contained in:
Stenzek
2023-12-05 00:21:01 +10:00
parent 601d8ff629
commit b166ec3403
4 changed files with 16 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/core/cpu_newrec_compiler_aarch32.cpp
View File

@ -1576,6 +1576,8 @@ void CPU::NewRec::AArch32Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize
const std::optional<VirtualMemoryAddress>& address)
{
DebugAssert(size == MemoryAccessSize::Word && !sign);
const Register addr = Register(AllocateTempHostReg(HR_CALLEE_SAVED));
FlushForLoadStore(address, false, use_fastmem);
// TODO: if address is constant, this can be simplified..
@ -1585,7 +1587,6 @@ void CPU::NewRec::AArch32Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize
UpdateLoadDelay();
// We'd need to be careful here if we weren't overwriting it..
const Register addr = Register(AllocateHostReg(HR_CALLEE_SAVED, HR_TYPE_TEMP));
ComputeLoadStoreAddressArg(cf, address, addr);
armAsm->and_(RARG1, addr, armCheckLogicalConstant(~0x3u));
GenerateLoad(RARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; });
@ -1768,11 +1769,12 @@ void CPU::NewRec::AArch32Compiler::Compile_swx(CompileFlags cf, MemoryAccessSize
const std::optional<VirtualMemoryAddress>& address)
{
DebugAssert(size == MemoryAccessSize::Word && !sign);
const Register addr = Register(AllocateTempHostReg(HR_CALLEE_SAVED));
FlushForLoadStore(address, true, use_fastmem);
// TODO: if address is constant, this can be simplified..
// We'd need to be careful here if we weren't overwriting it..
const Register addr = Register(AllocateHostReg(HR_CALLEE_SAVED, HR_TYPE_TEMP));
ComputeLoadStoreAddressArg(cf, address, addr);
armAsm->and_(RARG1, addr, armCheckLogicalConstant(~0x3u));
GenerateLoad(RARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; });