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CPU/NewRec: Add AArch32 backend

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This commit is contained in:
Stenzek
2023-10-21 16:23:01 +10:00
parent 8ddb0c4b23
commit b3cbe5a7ee
13 changed files with 2526 additions and 47 deletions
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8
src/core/cpu_newrec_compiler_aarch64.cpp
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@ -16,7 +16,7 @@
#include <limits>
Log_SetChannel(CPU::NewRec);
#define PTR(x) vixl::aarch64::MemOperand(RSTATE, (u32)(((u8*)(x)) - ((u8*)&g_state)))
#define PTR(x) vixl::aarch64::MemOperand(RSTATE, (((u8*)(x)) - ((u8*)&g_state)))
namespace CPU::NewRec {
@ -1019,10 +1019,10 @@ void CPU::NewRec::AArch64Compiler::Compile_div(CompileFlags cf)
Label done;
Label not_divide_by_zero;
armAsm->cbnz(rt, &not_divide_by_zero);
armAsm->cmp(rs, 0);
armAsm->mov(rhi, rs); // hi = num
EmitMov(rlo, 1);
EmitMov(RWSCRATCH, static_cast<u32>(-1));
armAsm->cmp(rs, 0);
armAsm->csel(rlo, RWSCRATCH, rlo, ge); // lo = s >= 0 ? -1 : 1
armAsm->b(&done);
@ -1328,7 +1328,7 @@ vixl::aarch64::WRegister CPU::NewRec::AArch64Compiler::GenerateLoad(const vixl::
{
DebugAssert(addr_reg.GetCode() != RWARG3.GetCode());
armAsm->lsr(RXARG3, addr_reg, Bus::FASTMEM_LUT_PAGE_SHIFT);
armAsm->ldr(RXARG3, MemOperand(RMEMBASE, RXARG3, LSL, 8));
armAsm->ldr(RXARG3, MemOperand(RMEMBASE, RXARG3, LSL, 3));
}
const MemOperand mem =
@ -1438,7 +1438,7 @@ void CPU::NewRec::AArch64Compiler::GenerateStore(const vixl::aarch64::WRegister&
{
DebugAssert(addr_reg.GetCode() != RWARG3.GetCode());
armAsm->lsr(RXARG3, addr_reg, Bus::FASTMEM_LUT_PAGE_SHIFT);
armAsm->ldr(RXARG3, MemOperand(RMEMBASE, RXARG3, LSL, 8));
armAsm->ldr(RXARG3, MemOperand(RMEMBASE, RXARG3, LSL, 3));
}
const MemOperand mem =