JIT optimizations and refactoring (#675)
* CPU/Recompiler: Use rel32 call where possible for no-args * JitCodeBuffer: Support using preallocated buffer * CPU/Recompiler/AArch64: Use bl instead of blr for short branches * CPU/CodeCache: Allocate recompiler buffer in program space This means we don't need 64-bit moves for every call out of the recompiler. * GTE: Don't store as u16 and load as u32 * CPU/Recompiler: Add methods to emit global load/stores * GTE: Convert class to namespace * CPU/Recompiler: Call GTE functions directly * Settings: Turn into a global variable * GPU: Replace local pointers with global * InterruptController: Turn into a global pointer * System: Replace local pointers with global * Timers: Turn into a global instance * DMA: Turn into a global instance * SPU: Turn into a global instance * CDROM: Turn into a global instance * MDEC: Turn into a global instance * Pad: Turn into a global instance * SIO: Turn into a global instance * CDROM: Move audio FIFO to the heap * CPU/Recompiler: Drop ASMFunctions No longer needed since we have code in the same 4GB window. * CPUCodeCache: Turn class into namespace * Bus: Local pointer -> global pointers * CPU: Turn class into namespace * Bus: Turn into namespace * GTE: Store registers in CPU state struct Allows relative addressing on ARM. * CPU/Recompiler: Align code storage to page size * CPU/Recompiler: Fix relative branches on A64 * HostInterface: Local references to global * System: Turn into a namespace, move events out * Add guard pages * Android: Fix build
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Connor McLaughlin
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@ -1,186 +1,105 @@
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#pragma once
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#include "common/bitfield.h"
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#include "cpu_types.h"
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#include "gte.h"
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#include "gte_types.h"
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#include "types.h"
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#include <array>
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#include <optional>
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class StateWrapper;
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class Bus;
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class System;
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namespace CPU {
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class CodeCache;
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namespace Recompiler {
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class CodeGenerator;
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class Thunks;
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} // namespace Recompiler
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class Core
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enum : VirtualMemoryAddress
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{
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public:
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static constexpr VirtualMemoryAddress RESET_VECTOR = UINT32_C(0xBFC00000);
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static constexpr PhysicalMemoryAddress DCACHE_LOCATION = UINT32_C(0x1F800000);
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static constexpr PhysicalMemoryAddress DCACHE_LOCATION_MASK = UINT32_C(0xFFFFFC00);
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static constexpr PhysicalMemoryAddress DCACHE_OFFSET_MASK = UINT32_C(0x000003FF);
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static constexpr PhysicalMemoryAddress DCACHE_SIZE = UINT32_C(0x00000400);
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friend CodeCache;
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friend Recompiler::CodeGenerator;
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friend Recompiler::Thunks;
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Core();
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~Core();
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void Initialize(Bus* bus);
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void Reset();
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bool DoState(StateWrapper& sw);
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void Execute();
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ALWAYS_INLINE Bus* GetBus() const { return m_bus; }
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ALWAYS_INLINE const Registers& GetRegs() const { return m_regs; }
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ALWAYS_INLINE Registers& GetRegs() { return m_regs; }
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ALWAYS_INLINE TickCount GetPendingTicks() const { return m_pending_ticks; }
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ALWAYS_INLINE void ResetPendingTicks() { m_pending_ticks = 0; }
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ALWAYS_INLINE void AddPendingTicks(TickCount ticks) { m_pending_ticks += ticks; }
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ALWAYS_INLINE TickCount GetDowncount() const { return m_downcount; }
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ALWAYS_INLINE void SetDowncount(TickCount downcount) { m_downcount = downcount; }
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ALWAYS_INLINE const GTE::Core& GetCop2() const { return m_cop2; }
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ALWAYS_INLINE GTE::Core& GetCop2() { return m_cop2; }
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// Sets the PC and flushes the pipeline.
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void SetPC(u32 new_pc);
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// Memory reads variants which do not raise exceptions.
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bool SafeReadMemoryByte(VirtualMemoryAddress addr, u8* value);
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bool SafeReadMemoryHalfWord(VirtualMemoryAddress addr, u16* value);
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bool SafeReadMemoryWord(VirtualMemoryAddress addr, u32* value);
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bool SafeWriteMemoryByte(VirtualMemoryAddress addr, u8 value);
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bool SafeWriteMemoryHalfWord(VirtualMemoryAddress addr, u16 value);
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bool SafeWriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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// External IRQs
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void SetExternalInterrupt(u8 bit);
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void ClearExternalInterrupt(u8 bit);
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private:
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template<MemoryAccessType type, MemoryAccessSize size>
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TickCount DoMemoryAccess(VirtualMemoryAddress address, u32& value);
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template<MemoryAccessType type, MemoryAccessSize size>
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bool DoAlignmentCheck(VirtualMemoryAddress address);
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template<MemoryAccessType type, MemoryAccessSize size>
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void DoScratchpadAccess(PhysicalMemoryAddress address, u32& value);
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bool ReadMemoryByte(VirtualMemoryAddress addr, u8* value);
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bool ReadMemoryHalfWord(VirtualMemoryAddress addr, u16* value);
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bool ReadMemoryWord(VirtualMemoryAddress addr, u32* value);
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bool WriteMemoryByte(VirtualMemoryAddress addr, u8 value);
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bool WriteMemoryHalfWord(VirtualMemoryAddress addr, u16 value);
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bool WriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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// state helpers
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ALWAYS_INLINE bool InUserMode() const { return m_cop0_regs.sr.KUc; }
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ALWAYS_INLINE bool InKernelMode() const { return !m_cop0_regs.sr.KUc; }
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void DisassembleAndPrint(u32 addr);
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void DisassembleAndLog(u32 addr);
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void DisassembleAndPrint(u32 addr, u32 instructions_before, u32 instructions_after);
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// Updates load delays - call after each instruction
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ALWAYS_INLINE void UpdateLoadDelay()
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{
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// the old value is needed in case the delay slot instruction overwrites the same register
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if (m_load_delay_reg != Reg::count)
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m_regs.r[static_cast<u8>(m_load_delay_reg)] = m_load_delay_value;
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m_load_delay_reg = m_next_load_delay_reg;
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m_load_delay_value = m_next_load_delay_value;
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m_next_load_delay_reg = Reg::count;
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}
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// Fetches the instruction at m_regs.npc
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bool FetchInstruction();
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void ExecuteInstruction();
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void ExecuteCop0Instruction();
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void ExecuteCop2Instruction();
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void Branch(u32 target);
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// exceptions
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u32 GetExceptionVector(Exception excode) const;
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void RaiseException(Exception excode);
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void RaiseException(Exception excode, u32 EPC, bool BD, bool BT, u8 CE);
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bool HasPendingInterrupt();
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void DispatchInterrupt();
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// clears pipeline of load/branch delays
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void FlushPipeline();
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// helper functions for registers which aren't writable
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u32 ReadReg(Reg rs);
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void WriteReg(Reg rd, u32 value);
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// helper for generating a load delay write
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void WriteRegDelayed(Reg rd, u32 value);
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// write to cache control register
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void WriteCacheControl(u32 value);
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// read/write cop0 regs
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std::optional<u32> ReadCop0Reg(Cop0Reg reg);
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void WriteCop0Reg(Cop0Reg reg, u32 value);
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Bus* m_bus = nullptr;
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// ticks the CPU has executed
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TickCount m_pending_ticks = 0;
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TickCount m_downcount = MAX_SLICE_SIZE;
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Registers m_regs = {};
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Cop0Registers m_cop0_regs = {};
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Instruction m_next_instruction = {};
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// address of the instruction currently being executed
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Instruction m_current_instruction = {};
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u32 m_current_instruction_pc = 0;
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bool m_current_instruction_in_branch_delay_slot = false;
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bool m_current_instruction_was_branch_taken = false;
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bool m_next_instruction_is_branch_delay_slot = false;
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bool m_branch_was_taken = false;
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bool m_exception_raised = false;
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bool m_interrupt_delay = false;
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// load delays
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Reg m_load_delay_reg = Reg::count;
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u32 m_load_delay_value = 0;
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Reg m_next_load_delay_reg = Reg::count;
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u32 m_next_load_delay_value = 0;
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u32 m_cache_control = 0;
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System* m_system = nullptr;
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// data cache (used as scratchpad)
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std::array<u8, DCACHE_SIZE> m_dcache = {};
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GTE::Core m_cop2;
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RESET_VECTOR = UINT32_C(0xBFC00000)
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};
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enum : PhysicalMemoryAddress
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{
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DCACHE_LOCATION = UINT32_C(0x1F800000),
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DCACHE_LOCATION_MASK = UINT32_C(0xFFFFFC00),
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DCACHE_OFFSET_MASK = UINT32_C(0x000003FF),
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DCACHE_SIZE = UINT32_C(0x00000400)
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};
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extern bool TRACE_EXECUTION;
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extern bool LOG_EXECUTION;
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struct State
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{
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// ticks the CPU has executed
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TickCount pending_ticks = 0;
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TickCount downcount = MAX_SLICE_SIZE;
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Registers regs = {};
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Cop0Registers cop0_regs = {};
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Instruction next_instruction = {};
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// address of the instruction currently being executed
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Instruction current_instruction = {};
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u32 current_instruction_pc = 0;
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bool current_instruction_in_branch_delay_slot = false;
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bool current_instruction_was_branch_taken = false;
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bool next_instruction_is_branch_delay_slot = false;
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bool branch_was_taken = false;
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bool exception_raised = false;
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bool interrupt_delay = false;
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bool frame_done = false;
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// load delays
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Reg load_delay_reg = Reg::count;
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u32 load_delay_value = 0;
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Reg next_load_delay_reg = Reg::count;
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u32 next_load_delay_value = 0;
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u32 cache_control = 0;
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// GTE registers are stored here so we can access them on ARM with a single instruction
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GTE::Regs gte_regs = {};
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// data cache (used as scratchpad)
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std::array<u8, DCACHE_SIZE> dcache = {};
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};
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extern State g_state;
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void Initialize();
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void Shutdown();
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void Reset();
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bool DoState(StateWrapper& sw);
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/// Executes interpreter loop.
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void Execute();
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ALWAYS_INLINE Registers& GetRegs() { return g_state.regs; }
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ALWAYS_INLINE TickCount GetPendingTicks() { return g_state.pending_ticks; }
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ALWAYS_INLINE void ResetPendingTicks() { g_state.pending_ticks = 0; }
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ALWAYS_INLINE void AddPendingTicks(TickCount ticks) { g_state.pending_ticks += ticks; }
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// state helpers
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ALWAYS_INLINE bool InUserMode() { return g_state.cop0_regs.sr.KUc; }
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ALWAYS_INLINE bool InKernelMode() { return !g_state.cop0_regs.sr.KUc; }
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// Memory reads variants which do not raise exceptions.
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bool SafeReadMemoryByte(VirtualMemoryAddress addr, u8* value);
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bool SafeReadMemoryHalfWord(VirtualMemoryAddress addr, u16* value);
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bool SafeReadMemoryWord(VirtualMemoryAddress addr, u32* value);
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bool SafeWriteMemoryByte(VirtualMemoryAddress addr, u8 value);
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bool SafeWriteMemoryHalfWord(VirtualMemoryAddress addr, u16 value);
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bool SafeWriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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// External IRQs
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void SetExternalInterrupt(u8 bit);
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void ClearExternalInterrupt(u8 bit);
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bool HasPendingInterrupt();
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void DispatchInterrupt();
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void DisassembleAndPrint(u32 addr);
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void DisassembleAndLog(u32 addr);
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void DisassembleAndPrint(u32 addr, u32 instructions_before, u32 instructions_after);
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// Write to CPU execution log file.
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void WriteToExecutionLog(const char* format, ...);
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} // namespace CPU
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extern bool TRACE_EXECUTION;
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extern bool LOG_EXECUTION;
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#include "cpu_core.inl"
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} // namespace CPU
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