CPU: Use partial icache fills for non-line-aligned addresses
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@ -25,13 +25,8 @@ enum : PhysicalMemoryAddress
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ICACHE_LINE_SIZE = 16,
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ICACHE_LINES = ICACHE_SIZE / ICACHE_LINE_SIZE,
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ICACHE_SLOTS_PER_LINE = ICACHE_SLOTS / ICACHE_LINES,
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ICACHE_TAG_ADDRESS_MASK = 0xFFFFFFF0u
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};
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enum : u32
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{
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ICACHE_DISABLED_BIT = 0x01,
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ICACHE_INVALD_BIT = 0x02,
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ICACHE_TAG_ADDRESS_MASK = 0xFFFFFFF0u,
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ICACHE_INVALID_BITS = 0x0Fu,
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};
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union CacheControl
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