CPU: Use partial icache fills for non-line-aligned addresses

This commit is contained in:
Connor McLaughlin
2020-10-29 23:04:36 +10:00
parent 3b3ad0c1cb
commit be63d893cd
4 changed files with 46 additions and 34 deletions

View File

@ -25,13 +25,8 @@ enum : PhysicalMemoryAddress
ICACHE_LINE_SIZE = 16,
ICACHE_LINES = ICACHE_SIZE / ICACHE_LINE_SIZE,
ICACHE_SLOTS_PER_LINE = ICACHE_SLOTS / ICACHE_LINES,
ICACHE_TAG_ADDRESS_MASK = 0xFFFFFFF0u
};
enum : u32
{
ICACHE_DISABLED_BIT = 0x01,
ICACHE_INVALD_BIT = 0x02,
ICACHE_TAG_ADDRESS_MASK = 0xFFFFFFF0u,
ICACHE_INVALID_BITS = 0x0Fu,
};
union CacheControl