Refactor timing to allow sync/updates in the middle of a slice
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@ -26,7 +26,8 @@ bool Core::Initialize(Bus* bus)
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void Core::Reset()
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{
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m_slice_ticks = std::numeric_limits<decltype(m_slice_ticks)>::max();
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m_pending_ticks = 0;
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m_downcount = MAX_SLICE_SIZE;
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m_regs = {};
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@ -47,7 +48,8 @@ void Core::Reset()
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bool Core::DoState(StateWrapper& sw)
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{
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sw.Do(&m_slice_ticks);
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sw.Do(&m_pending_ticks);
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sw.Do(&m_downcount);
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sw.DoArray(m_regs.r, countof(m_regs.r));
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sw.Do(&m_regs.pc);
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sw.Do(&m_regs.hi);
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@ -312,12 +314,12 @@ void Core::DisassembleAndPrint(u32 addr)
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PrintInstruction(bits, addr);
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}
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TickCount Core::Execute()
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void Core::Execute()
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{
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TickCount executed_ticks = 0;
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while (executed_ticks < m_slice_ticks)
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while (m_downcount >= 0)
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{
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executed_ticks++;
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m_pending_ticks += 3;
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m_downcount -= 3;
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// now executing the instruction we previously fetched
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const Instruction inst = m_next_instruction;
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@ -340,10 +342,6 @@ TickCount Core::Execute()
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m_load_delay_old_value = m_next_load_delay_old_value;
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m_next_load_delay_old_value = 0;
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}
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// reset slice ticks, it'll be updated when the components execute
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m_slice_ticks = MAX_CPU_SLICE_SIZE;
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return executed_ticks;
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}
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bool Core::FetchInstruction()
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