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Refactor timing to allow sync/updates in the middle of a slice

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This commit is contained in:
Connor McLaughlin
2019-09-20 23:59:48 +10:00
parent ad316162f3
commit c988af453c
10 changed files with 74 additions and 36 deletions
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13
src/pse/cpu_core.h
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@ -27,12 +27,16 @@ public:
void Reset();
bool DoState(StateWrapper& sw);
TickCount Execute();
void Execute();
const Registers& GetRegs() const { return m_regs; }
Registers& GetRegs() { return m_regs; }
void SetSliceTicks(TickCount downcount) { m_slice_ticks = (downcount < m_slice_ticks ? downcount : m_slice_ticks); }
TickCount GetPendingTicks() const { return m_pending_ticks; }
void ResetPendingTicks() { m_pending_ticks = 0; }
void SetDowncount(TickCount downcount) { m_downcount = (downcount < m_downcount) ? downcount : m_downcount; }
void ResetDowncount() { m_downcount = MAX_SLICE_SIZE; }
// Sets the PC and flushes the pipeline.
void SetPC(u32 new_pc);
@ -101,8 +105,9 @@ private:
Bus* m_bus = nullptr;
// ticks of master/CPU clock until the next event
TickCount m_slice_ticks = 0;
// ticks the CPU has executed
TickCount m_pending_ticks = 0;
TickCount m_downcount = MAX_SLICE_SIZE;
Registers m_regs = {};
Cop0Registers m_cop0_regs = {};