dep: Add vixl (AArch32/64 assembler)
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Connor McLaughlin
178
dep/vixl/src/aarch64/cpu-aarch64.cc
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178
dep/vixl/src/aarch64/cpu-aarch64.cc
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// Copyright 2015, VIXL authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include "../utils-vixl.h"
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#include "cpu-aarch64.h"
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namespace vixl {
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namespace aarch64 {
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// Initialise to smallest possible cache size.
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unsigned CPU::dcache_line_size_ = 1;
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unsigned CPU::icache_line_size_ = 1;
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// Currently computes I and D cache line size.
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void CPU::SetUp() {
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uint32_t cache_type_register = GetCacheType();
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// The cache type register holds information about the caches, including I
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// D caches line size.
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static const int kDCacheLineSizeShift = 16;
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static const int kICacheLineSizeShift = 0;
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static const uint32_t kDCacheLineSizeMask = 0xf << kDCacheLineSizeShift;
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static const uint32_t kICacheLineSizeMask = 0xf << kICacheLineSizeShift;
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// The cache type register holds the size of the I and D caches in words as
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// a power of two.
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uint32_t dcache_line_size_power_of_two =
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(cache_type_register & kDCacheLineSizeMask) >> kDCacheLineSizeShift;
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uint32_t icache_line_size_power_of_two =
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(cache_type_register & kICacheLineSizeMask) >> kICacheLineSizeShift;
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dcache_line_size_ = 4 << dcache_line_size_power_of_two;
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icache_line_size_ = 4 << icache_line_size_power_of_two;
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}
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uint32_t CPU::GetCacheType() {
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#ifdef __aarch64__
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uint64_t cache_type_register;
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// Copy the content of the cache type register to a core register.
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__asm__ __volatile__("mrs %[ctr], ctr_el0" // NOLINT(runtime/references)
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: [ctr] "=r"(cache_type_register));
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VIXL_ASSERT(IsUint32(cache_type_register));
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return static_cast<uint32_t>(cache_type_register);
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#else
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// This will lead to a cache with 1 byte long lines, which is fine since
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// neither EnsureIAndDCacheCoherency nor the simulator will need this
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// information.
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return 0;
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#endif
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}
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void CPU::EnsureIAndDCacheCoherency(void *address, size_t length) {
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#ifdef __aarch64__
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// Implement the cache synchronisation for all targets where AArch64 is the
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// host, even if we're building the simulator for an AAarch64 host. This
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// allows for cases where the user wants to simulate code as well as run it
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// natively.
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if (length == 0) {
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return;
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}
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// The code below assumes user space cache operations are allowed.
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// Work out the line sizes for each cache, and use them to determine the
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// start addresses.
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uintptr_t start = reinterpret_cast<uintptr_t>(address);
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uintptr_t dsize = static_cast<uintptr_t>(dcache_line_size_);
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uintptr_t isize = static_cast<uintptr_t>(icache_line_size_);
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uintptr_t dline = start & ~(dsize - 1);
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uintptr_t iline = start & ~(isize - 1);
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// Cache line sizes are always a power of 2.
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VIXL_ASSERT(IsPowerOf2(dsize));
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VIXL_ASSERT(IsPowerOf2(isize));
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uintptr_t end = start + length;
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do {
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__asm__ __volatile__(
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// Clean each line of the D cache containing the target data.
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//
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// dc : Data Cache maintenance
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// c : Clean
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// va : by (Virtual) Address
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// u : to the point of Unification
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// The point of unification for a processor is the point by which the
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// instruction and data caches are guaranteed to see the same copy of a
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// memory location. See ARM DDI 0406B page B2-12 for more information.
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" dc cvau, %[dline]\n"
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:
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: [dline] "r"(dline)
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// This code does not write to memory, but the "memory" dependency
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// prevents GCC from reordering the code.
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: "memory");
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dline += dsize;
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} while (dline < end);
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__asm__ __volatile__(
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// Make sure that the data cache operations (above) complete before the
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// instruction cache operations (below).
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//
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// dsb : Data Synchronisation Barrier
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// ish : Inner SHareable domain
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//
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// The point of unification for an Inner Shareable shareability domain is
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// the point by which the instruction and data caches of all the
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// processors
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// in that Inner Shareable shareability domain are guaranteed to see the
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// same copy of a memory location. See ARM DDI 0406B page B2-12 for more
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// information.
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" dsb ish\n"
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:
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:
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: "memory");
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do {
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__asm__ __volatile__(
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// Invalidate each line of the I cache containing the target data.
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//
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// ic : Instruction Cache maintenance
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// i : Invalidate
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// va : by Address
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// u : to the point of Unification
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" ic ivau, %[iline]\n"
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:
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: [iline] "r"(iline)
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: "memory");
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iline += isize;
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} while (iline < end);
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__asm__ __volatile__(
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// Make sure that the instruction cache operations (above) take effect
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// before the isb (below).
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" dsb ish\n"
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// Ensure that any instructions already in the pipeline are discarded and
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// reloaded from the new data.
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// isb : Instruction Synchronisation Barrier
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" isb\n"
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:
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:
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: "memory");
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#else
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// If the host isn't AArch64, we must be using the simulator, so this function
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// doesn't have to do anything.
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USE(address, length);
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#endif
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}
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} // namespace aarch64
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} // namespace vixl
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