CPU: Correct bits for CAUSE.CE, EPC for fetch
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@ -75,17 +75,19 @@ private:
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bool InKernelMode() const { return !m_cop0_regs.sr.KUc; }
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void DisassembleAndPrint(u32 addr);
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void DisassembleAndPrint(u32 addr, u32 instructions_before, u32 instructions_after);
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// Fetches the instruction at m_regs.npc
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bool FetchInstruction();
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void ExecuteInstruction(Instruction inst);
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void ExecuteCop0Instruction(Instruction inst);
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void ExecuteCop2Instruction(Instruction inst);
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void ExecuteInstruction();
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void ExecuteCop0Instruction();
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void ExecuteCop2Instruction();
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void Branch(u32 target);
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// exceptions
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u32 GetExceptionVector(Exception excode) const;
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void RaiseException(Exception excode, u8 coprocessor = 0);
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void RaiseException(Exception excode);
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void RaiseException(Exception excode, u32 EPC, bool BD, u8 CE);
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bool DispatchInterrupts();
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// flushes any load delays if present
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@ -119,6 +121,7 @@ private:
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Instruction m_next_instruction = {};
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// address of the instruction currently being executed
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Instruction m_current_instruction = {};
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u32 m_current_instruction_pc = 0;
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// load delays
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