Misc: Build fixes for Android
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@ -125,12 +125,12 @@ ALWAYS_INLINE_RELEASE void MaskValidate(PGXP_value* pV, u32 psxV, u32 mask, u32
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ALWAYS_INLINE_RELEASE double f16Sign(double in)
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{
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u32 s = (u32)(in * (double)((u32)1 << 16));
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return ((double)*((s32*)&s)) / (double)((s32)1 << 16);
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const s32 s = static_cast<s32>(static_cast<u64>(in * (USHRT_MAX + 1)));
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return static_cast<double>(s) / static_cast<double>(USHRT_MAX + 1);
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}
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ALWAYS_INLINE_RELEASE double f16Unsign(double in)
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{
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return (in >= 0) ? in : ((double)in + (double)USHRT_MAX + 1);
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return (in >= 0) ? in : (in + (USHRT_MAX + 1));
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}
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ALWAYS_INLINE_RELEASE double f16Overflow(double in)
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{
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@ -599,13 +599,11 @@ void CPU_MOVE(u32 rd_and_rs, u32 rsVal)
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void CPU_ADDI(u32 instr, u32 rsVal)
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{
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// Rt = Rs + Imm (signed)
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psx_value tempImm;
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PGXP_value ret;
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Validate(&CPU_reg[rs(instr)], rsVal);
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ret = CPU_reg[rs(instr)];
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tempImm.d = imm(instr);
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tempImm.sd = (tempImm.sd << 16) >> 16; // sign extend
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PGXP_value ret = CPU_reg[rs(instr)];
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psx_value tempImm;
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tempImm.d = SignExtend32(static_cast<u16>(imm(instr)));
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if (tempImm.d != 0)
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{
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@ -929,6 +927,11 @@ static void CPU_BITWISE(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
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ret.z = CPU_reg[rt(instr)].z;
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ret.compFlags[2] = CPU_reg[rt(instr)].compFlags[2];
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}
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else
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{
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ret.z = 0.0f;
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ret.compFlags[2] = 0;
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}
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ret.value = rdVal;
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CPU_reg[rd(instr)] = ret;
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