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Dep: Update vixl to 662828c

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This commit is contained in:
Stenzek
2024-06-14 17:27:12 +10:00
parent d45e218da7
commit f0c2832d03
66 changed files with 65453 additions and 10345 deletions
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804
dep/vixl/src/aarch64/cpu-features-auditor-aarch64.cc
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@@ -24,16 +24,54 @@
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include "cpu-features-auditor-aarch64.h"
#include "cpu-features.h"
#include "globals-vixl.h"
#include "utils-vixl.h"
#include "decoder-aarch64.h"
#include "cpu-features-auditor-aarch64.h"
#include "decoder-aarch64.h"
namespace vixl {
namespace aarch64 {
const CPUFeaturesAuditor::FormToVisitorFnMap*
CPUFeaturesAuditor::GetFormToVisitorFnMap() {
static const FormToVisitorFnMap form_to_visitor = {
DEFAULT_FORM_TO_VISITOR_MAP(CPUFeaturesAuditor),
SIM_AUD_VISITOR_MAP(CPUFeaturesAuditor),
{"fcmla_asimdelem_c_h"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fcmla_asimdelem_c_s"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fmlal2_asimdelem_lh"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fmlal_asimdelem_lh"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fmla_asimdelem_rh_h"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fmla_asimdelem_r_sd"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fmlsl2_asimdelem_lh"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fmlsl_asimdelem_lh"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fmls_asimdelem_rh_h"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fmls_asimdelem_r_sd"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fmulx_asimdelem_rh_h"_h,
&CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fmulx_asimdelem_r_sd"_h,
&CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fmul_asimdelem_rh_h"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"fmul_asimdelem_r_sd"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"sdot_asimdelem_d"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"smlal_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"smlsl_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"smull_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"sqdmlal_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"sqdmlsl_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"sqdmull_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"udot_asimdelem_d"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"umlal_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"umlsl_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
{"umull_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
};
return &form_to_visitor;
}
// Every instruction must update last_instruction_, even if only to clear it,
// and every instruction must also update seen_ once it has been fully handled.
// This scope makes that simple, and allows early returns in the decode logic.
@@ -140,6 +178,25 @@ void CPUFeaturesAuditor::VisitAddSubWithCarry(const Instruction* instr) {
USE(instr);
}
void CPUFeaturesAuditor::VisitRotateRightIntoFlags(const Instruction* instr) {
RecordInstructionFeaturesScope scope(this);
switch (instr->Mask(RotateRightIntoFlagsMask)) {
case RMIF:
scope.Record(CPUFeatures::kFlagM);
return;
}
}
void CPUFeaturesAuditor::VisitEvaluateIntoFlags(const Instruction* instr) {
RecordInstructionFeaturesScope scope(this);
switch (instr->Mask(EvaluateIntoFlagsMask)) {
case SETF8:
case SETF16:
scope.Record(CPUFeatures::kFlagM);
return;
}
}
void CPUFeaturesAuditor::VisitAtomicMemory(const Instruction* instr) {
RecordInstructionFeaturesScope scope(this);
switch (instr->Mask(AtomicMemoryMask)) {
@@ -254,6 +311,37 @@ void CPUFeaturesAuditor::VisitDataProcessing2Source(const Instruction* instr) {
}
}
void CPUFeaturesAuditor::VisitLoadStoreRCpcUnscaledOffset(
const Instruction* instr) {
RecordInstructionFeaturesScope scope(this);
switch (instr->Mask(LoadStoreRCpcUnscaledOffsetMask)) {
case LDAPURB:
case LDAPURSB_w:
case LDAPURSB_x:
case LDAPURH:
case LDAPURSH_w:
case LDAPURSH_x:
case LDAPUR_w:
case LDAPURSW:
case LDAPUR_x:
// These stores don't actually have RCpc semantics but they're included with
// the RCpc extensions.
case STLURB:
case STLURH:
case STLUR_w:
case STLUR_x:
scope.Record(CPUFeatures::kRCpc, CPUFeatures::kRCpcImm);
return;
}
}
void CPUFeaturesAuditor::VisitLoadStorePAC(const Instruction* instr) {
RecordInstructionFeaturesScope scope(this);
USE(instr);
scope.Record(CPUFeatures::kPAuth);
}
void CPUFeaturesAuditor::VisitDataProcessing3Source(const Instruction* instr) {
RecordInstructionFeaturesScope scope(this);
USE(instr);
@@ -329,6 +417,16 @@ void CPUFeaturesAuditor::VisitFPDataProcessing1Source(
case FRINTI_h:
scope.Record(CPUFeatures::kFPHalf);
return;
case FRINT32X_s:
case FRINT32X_d:
case FRINT32Z_s:
case FRINT32Z_d:
case FRINT64X_s:
case FRINT64X_d:
case FRINT64Z_s:
case FRINT64Z_d:
scope.Record(CPUFeatures::kFrintToFixedSizedInt);
return;
default:
// No special CPU features.
// This category includes some half-precision FCVT instructions that do
@@ -410,8 +508,6 @@ void CPUFeaturesAuditor::VisitFPImmediate(const Instruction* instr) {
void CPUFeaturesAuditor::VisitFPIntegerConvert(const Instruction* instr) {
RecordInstructionFeaturesScope scope(this);
// All of these instructions require FP.
scope.Record(CPUFeatures::kFP);
switch (instr->Mask(FPIntegerConvertMask)) {
case FCVTAS_wh:
case FCVTAS_xh:
@@ -441,17 +537,23 @@ void CPUFeaturesAuditor::VisitFPIntegerConvert(const Instruction* instr) {
case SCVTF_hx:
case UCVTF_hw:
case UCVTF_hx:
scope.Record(CPUFeatures::kFP);
scope.Record(CPUFeatures::kFPHalf);
return;
case FMOV_dx:
scope.RecordOneOrBothOf(CPUFeatures::kFP, CPUFeatures::kNEON);
return;
case FMOV_d1_x:
case FMOV_x_d1:
scope.Record(CPUFeatures::kFP);
scope.Record(CPUFeatures::kNEON);
return;
case FJCVTZS:
scope.Record(CPUFeatures::kFP);
scope.Record(CPUFeatures::kJSCVT);
return;
default:
// No special CPU features.
scope.Record(CPUFeatures::kFP);
return;
}
}
@@ -611,6 +713,12 @@ void CPUFeaturesAuditor::VisitNEON2RegMisc(const Instruction* instr) {
case NEON_FCMLT_zero:
scope.Record(CPUFeatures::kFP);
return;
case NEON_FRINT32X:
case NEON_FRINT32Z:
case NEON_FRINT64X:
case NEON_FRINT64Z:
scope.Record(CPUFeatures::kFP, CPUFeatures::kFrintToFixedSizedInt);
return;
default:
// No additional features.
return;
@@ -628,6 +736,12 @@ void CPUFeaturesAuditor::VisitNEON3Different(const Instruction* instr) {
RecordInstructionFeaturesScope scope(this);
// All of these instructions require NEON.
scope.Record(CPUFeatures::kNEON);
if (form_hash_ == "pmull_asimddiff_l"_h) {
if (instr->GetNEONSize() == 3) {
// Source is 1D or 2D, destination is 1Q.
scope.Record(CPUFeatures::kPmull1Q);
}
}
USE(instr);
}
@@ -638,6 +752,17 @@ void CPUFeaturesAuditor::VisitNEON3Same(const Instruction* instr) {
if (instr->Mask(NEON3SameFPFMask) == NEON3SameFPFixed) {
scope.Record(CPUFeatures::kFP);
}
switch (instr->Mask(NEON3SameFHMMask)) {
case NEON_FMLAL:
case NEON_FMLAL2:
case NEON_FMLSL:
case NEON_FMLSL2:
scope.Record(CPUFeatures::kFP, CPUFeatures::kNEONHalf, CPUFeatures::kFHM);
return;
default:
// No additional features.
return;
}
}
void CPUFeaturesAuditor::VisitNEON3SameExtra(const Instruction* instr) {
@@ -699,7 +824,18 @@ void CPUFeaturesAuditor::VisitNEONByIndexedElement(const Instruction* instr) {
scope.Record(CPUFeatures::kRDM);
return;
default:
// Fall through to check other FP instructions.
// Fall through to check other instructions.
break;
}
switch (instr->Mask(NEONByIndexedElementFPLongMask)) {
case NEON_FMLAL_H_byelement:
case NEON_FMLAL2_H_byelement:
case NEON_FMLSL_H_byelement:
case NEON_FMLSL2_H_byelement:
scope.Record(CPUFeatures::kFP, CPUFeatures::kNEONHalf, CPUFeatures::kFHM);
return;
default:
// Fall through to check other instructions.
break;
}
switch (instr->Mask(NEONByIndexedElementFPMask)) {
@@ -782,7 +918,6 @@ void CPUFeaturesAuditor::VisitNEONModifiedImmediate(const Instruction* instr) {
scope.Record(CPUFeatures::kFP);
if (instr->ExtractBit(11)) scope.Record(CPUFeatures::kNEONHalf);
}
USE(instr);
}
void CPUFeaturesAuditor::VisitNEONPerm(const Instruction* instr) {
@@ -980,6 +1115,165 @@ void CPUFeaturesAuditor::VisitPCRelAddressing(const Instruction* instr) {
USE(instr);
}
// Most SVE visitors require only SVE.
#define VIXL_SIMPLE_SVE_VISITOR_LIST(V) \
V(SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets) \
V(SVE32BitGatherLoad_VectorPlusImm) \
V(SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets) \
V(SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets) \
V(SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets) \
V(SVE32BitGatherPrefetch_VectorPlusImm) \
V(SVE32BitScatterStore_ScalarPlus32BitScaledOffsets) \
V(SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets) \
V(SVE32BitScatterStore_VectorPlusImm) \
V(SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets) \
V(SVE64BitGatherLoad_ScalarPlus64BitScaledOffsets) \
V(SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets) \
V(SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets) \
V(SVE64BitGatherLoad_VectorPlusImm) \
V(SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets) \
V(SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets) \
V(SVE64BitGatherPrefetch_VectorPlusImm) \
V(SVE64BitScatterStore_ScalarPlus64BitScaledOffsets) \
V(SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets) \
V(SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets) \
V(SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets) \
V(SVE64BitScatterStore_VectorPlusImm) \
V(SVEAddressGeneration) \
V(SVEBitwiseLogicalUnpredicated) \
V(SVEBitwiseShiftUnpredicated) \
V(SVEFFRInitialise) \
V(SVEFFRWriteFromPredicate) \
V(SVEFPAccumulatingReduction) \
V(SVEFPArithmeticUnpredicated) \
V(SVEFPCompareVectors) \
V(SVEFPCompareWithZero) \
V(SVEFPComplexAddition) \
V(SVEFPComplexMulAdd) \
V(SVEFPComplexMulAddIndex) \
V(SVEFPFastReduction) \
V(SVEFPMulIndex) \
V(SVEFPMulAdd) \
V(SVEFPMulAddIndex) \
V(SVEFPUnaryOpUnpredicated) \
V(SVEIncDecByPredicateCount) \
V(SVEIndexGeneration) \
V(SVEIntArithmeticUnpredicated) \
V(SVEIntCompareSignedImm) \
V(SVEIntCompareUnsignedImm) \
V(SVEIntCompareVectors) \
V(SVEIntMulAddPredicated) \
V(SVEIntMulAddUnpredicated) \
V(SVEIntReduction) \
V(SVEIntUnaryArithmeticPredicated) \
V(SVEMovprfx) \
V(SVEMulIndex) \
V(SVEPermuteVectorExtract) \
V(SVEPermuteVectorInterleaving) \
V(SVEPredicateCount) \
V(SVEPredicateLogical) \
V(SVEPropagateBreak) \
V(SVEStackFrameAdjustment) \
V(SVEStackFrameSize) \
V(SVEVectorSelect) \
V(SVEBitwiseLogical_Predicated) \
V(SVEBitwiseLogicalWithImm_Unpredicated) \
V(SVEBitwiseShiftByImm_Predicated) \
V(SVEBitwiseShiftByVector_Predicated) \
V(SVEBitwiseShiftByWideElements_Predicated) \
V(SVEBroadcastBitmaskImm) \
V(SVEBroadcastFPImm_Unpredicated) \
V(SVEBroadcastGeneralRegister) \
V(SVEBroadcastIndexElement) \
V(SVEBroadcastIntImm_Unpredicated) \
V(SVECompressActiveElements) \
V(SVEConditionallyBroadcastElementToVector) \
V(SVEConditionallyExtractElementToSIMDFPScalar) \
V(SVEConditionallyExtractElementToGeneralRegister) \
V(SVEConditionallyTerminateScalars) \
V(SVEConstructivePrefix_Unpredicated) \
V(SVEContiguousFirstFaultLoad_ScalarPlusScalar) \
V(SVEContiguousLoad_ScalarPlusImm) \
V(SVEContiguousLoad_ScalarPlusScalar) \
V(SVEContiguousNonFaultLoad_ScalarPlusImm) \
V(SVEContiguousNonTemporalLoad_ScalarPlusImm) \
V(SVEContiguousNonTemporalLoad_ScalarPlusScalar) \
V(SVEContiguousNonTemporalStore_ScalarPlusImm) \
V(SVEContiguousNonTemporalStore_ScalarPlusScalar) \
V(SVEContiguousPrefetch_ScalarPlusImm) \
V(SVEContiguousPrefetch_ScalarPlusScalar) \
V(SVEContiguousStore_ScalarPlusImm) \
V(SVEContiguousStore_ScalarPlusScalar) \
V(SVECopySIMDFPScalarRegisterToVector_Predicated) \
V(SVECopyFPImm_Predicated) \
V(SVECopyGeneralRegisterToVector_Predicated) \
V(SVECopyIntImm_Predicated) \
V(SVEElementCount) \
V(SVEExtractElementToSIMDFPScalarRegister) \
V(SVEExtractElementToGeneralRegister) \
V(SVEFPArithmetic_Predicated) \
V(SVEFPArithmeticWithImm_Predicated) \
V(SVEFPConvertPrecision) \
V(SVEFPConvertToInt) \
V(SVEFPExponentialAccelerator) \
V(SVEFPRoundToIntegralValue) \
V(SVEFPTrigMulAddCoefficient) \
V(SVEFPTrigSelectCoefficient) \
V(SVEFPUnaryOp) \
V(SVEIncDecRegisterByElementCount) \
V(SVEIncDecVectorByElementCount) \
V(SVEInsertSIMDFPScalarRegister) \
V(SVEInsertGeneralRegister) \
V(SVEIntAddSubtractImm_Unpredicated) \
V(SVEIntAddSubtractVectors_Predicated) \
V(SVEIntCompareScalarCountAndLimit) \
V(SVEIntConvertToFP) \
V(SVEIntDivideVectors_Predicated) \
V(SVEIntMinMaxImm_Unpredicated) \
V(SVEIntMinMaxDifference_Predicated) \
V(SVEIntMulImm_Unpredicated) \
V(SVEIntMulVectors_Predicated) \
V(SVELoadAndBroadcastElement) \
V(SVELoadAndBroadcastQOWord_ScalarPlusImm) \
V(SVELoadAndBroadcastQOWord_ScalarPlusScalar) \
V(SVELoadMultipleStructures_ScalarPlusImm) \
V(SVELoadMultipleStructures_ScalarPlusScalar) \
V(SVELoadPredicateRegister) \
V(SVELoadVectorRegister) \
V(SVEPartitionBreakCondition) \
V(SVEPermutePredicateElements) \
V(SVEPredicateFirstActive) \
V(SVEPredicateInitialize) \
V(SVEPredicateNextActive) \
V(SVEPredicateReadFromFFR_Predicated) \
V(SVEPredicateReadFromFFR_Unpredicated) \
V(SVEPredicateTest) \
V(SVEPredicateZero) \
V(SVEPropagateBreakToNextPartition) \
V(SVEReversePredicateElements) \
V(SVEReverseVectorElements) \
V(SVEReverseWithinElements) \
V(SVESaturatingIncDecRegisterByElementCount) \
V(SVESaturatingIncDecVectorByElementCount) \
V(SVEStoreMultipleStructures_ScalarPlusImm) \
V(SVEStoreMultipleStructures_ScalarPlusScalar) \
V(SVEStorePredicateRegister) \
V(SVEStoreVectorRegister) \
V(SVETableLookup) \
V(SVEUnpackPredicateElements) \
V(SVEUnpackVectorElements) \
V(SVEVectorSplice)
#define VIXL_DEFINE_SIMPLE_SVE_VISITOR(NAME) \
void CPUFeaturesAuditor::Visit##NAME(const Instruction* instr) { \
RecordInstructionFeaturesScope scope(this); \
scope.Record(CPUFeatures::kSVE); \
USE(instr); \
}
VIXL_SIMPLE_SVE_VISITOR_LIST(VIXL_DEFINE_SIMPLE_SVE_VISITOR)
#undef VIXL_DEFINE_SIMPLE_SVE_VISITOR
#undef VIXL_SIMPLE_SVE_VISITOR_LIST
void CPUFeaturesAuditor::VisitSystem(const Instruction* instr) {
RecordInstructionFeaturesScope scope(this);
if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
@@ -1001,7 +1295,19 @@ void CPUFeaturesAuditor::VisitSystem(const Instruction* instr) {
required.Combine(CPUFeatures::kPAuth);
break;
default:
if (instr->GetImmHint() == ESB) required.Combine(CPUFeatures::kRAS);
switch (instr->GetImmHint()) {
case ESB:
required.Combine(CPUFeatures::kRAS);
break;
case BTI:
case BTI_j:
case BTI_c:
case BTI_jc:
required.Combine(CPUFeatures::kBTI);
break;
default:
break;
}
break;
}
@@ -1009,6 +1315,52 @@ void CPUFeaturesAuditor::VisitSystem(const Instruction* instr) {
// features are not implemented, so we record the corresponding features
// only if they are available.
if (available_.Has(required)) scope.Record(required);
} else if (instr->Mask(SystemSysMask) == SYS) {
switch (instr->GetSysOp()) {
// DC instruction variants.
case CGVAC:
case CGDVAC:
case CGVAP:
case CGDVAP:
case CIGVAC:
case CIGDVAC:
case GVA:
case GZVA:
scope.Record(CPUFeatures::kMTE);
break;
case CVAP:
scope.Record(CPUFeatures::kDCPoP);
break;
case CVADP:
scope.Record(CPUFeatures::kDCCVADP);
break;
case IVAU:
case CVAC:
case CVAU:
case CIVAC:
case ZVA:
// No special CPU features.
break;
}
} else if (instr->Mask(SystemPStateFMask) == SystemPStateFixed) {
switch (instr->Mask(SystemPStateMask)) {
case CFINV:
scope.Record(CPUFeatures::kFlagM);
break;
case AXFLAG:
case XAFLAG:
scope.Record(CPUFeatures::kAXFlag);
break;
}
} else if (instr->Mask(SystemSysRegFMask) == SystemSysRegFixed) {
if (instr->Mask(SystemSysRegMask) == MRS) {
switch (instr->GetImmSystemRegister()) {
case RNDR:
case RNDRRS:
scope.Record(CPUFeatures::kRNG);
break;
}
}
}
}
@@ -1049,11 +1401,447 @@ void CPUFeaturesAuditor::VisitUnconditionalBranchToRegister(
}
}
void CPUFeaturesAuditor::VisitReserved(const Instruction* instr) {
RecordInstructionFeaturesScope scope(this);
USE(instr);
}
void CPUFeaturesAuditor::VisitUnimplemented(const Instruction* instr) {
RecordInstructionFeaturesScope scope(this);
USE(instr);
}
void CPUFeaturesAuditor::Visit(Metadata* metadata, const Instruction* instr) {
VIXL_ASSERT(metadata->count("form") > 0);
const std::string& form = (*metadata)["form"];
form_hash_ = Hash(form.c_str());
const FormToVisitorFnMap* fv = CPUFeaturesAuditor::GetFormToVisitorFnMap();
FormToVisitorFnMap::const_iterator it = fv->find(form_hash_);
if (it == fv->end()) {
RecordInstructionFeaturesScope scope(this);
std::map<uint32_t, const CPUFeatures> features = {
{"adclb_z_zzz"_h, CPUFeatures::kSVE2},
{"adclt_z_zzz"_h, CPUFeatures::kSVE2},
{"addhnb_z_zz"_h, CPUFeatures::kSVE2},
{"addhnt_z_zz"_h, CPUFeatures::kSVE2},
{"addp_z_p_zz"_h, CPUFeatures::kSVE2},
{"bcax_z_zzz"_h, CPUFeatures::kSVE2},
{"bdep_z_zz"_h,
CPUFeatures(CPUFeatures::kSVE2, CPUFeatures::kSVEBitPerm)},
{"bext_z_zz"_h,
CPUFeatures(CPUFeatures::kSVE2, CPUFeatures::kSVEBitPerm)},
{"bgrp_z_zz"_h,
CPUFeatures(CPUFeatures::kSVE2, CPUFeatures::kSVEBitPerm)},
{"bsl1n_z_zzz"_h, CPUFeatures::kSVE2},
{"bsl2n_z_zzz"_h, CPUFeatures::kSVE2},
{"bsl_z_zzz"_h, CPUFeatures::kSVE2},
{"cadd_z_zz"_h, CPUFeatures::kSVE2},
{"cdot_z_zzz"_h, CPUFeatures::kSVE2},
{"cdot_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"cdot_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"cmla_z_zzz"_h, CPUFeatures::kSVE2},
{"cmla_z_zzzi_h"_h, CPUFeatures::kSVE2},
{"cmla_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"eor3_z_zzz"_h, CPUFeatures::kSVE2},
{"eorbt_z_zz"_h, CPUFeatures::kSVE2},
{"eortb_z_zz"_h, CPUFeatures::kSVE2},
{"ext_z_zi_con"_h, CPUFeatures::kSVE2},
{"faddp_z_p_zz"_h, CPUFeatures::kSVE2},
{"fcvtlt_z_p_z_h2s"_h, CPUFeatures::kSVE2},
{"fcvtlt_z_p_z_s2d"_h, CPUFeatures::kSVE2},
{"fcvtnt_z_p_z_d2s"_h, CPUFeatures::kSVE2},
{"fcvtnt_z_p_z_s2h"_h, CPUFeatures::kSVE2},
{"fcvtx_z_p_z_d2s"_h, CPUFeatures::kSVE2},
{"fcvtxnt_z_p_z_d2s"_h, CPUFeatures::kSVE2},
{"flogb_z_p_z"_h, CPUFeatures::kSVE2},
{"fmaxnmp_z_p_zz"_h, CPUFeatures::kSVE2},
{"fmaxp_z_p_zz"_h, CPUFeatures::kSVE2},
{"fminnmp_z_p_zz"_h, CPUFeatures::kSVE2},
{"fminp_z_p_zz"_h, CPUFeatures::kSVE2},
{"fmlalb_z_zzz"_h, CPUFeatures::kSVE2},
{"fmlalb_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"fmlalt_z_zzz"_h, CPUFeatures::kSVE2},
{"fmlalt_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"fmlslb_z_zzz"_h, CPUFeatures::kSVE2},
{"fmlslb_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"fmlslt_z_zzz"_h, CPUFeatures::kSVE2},
{"fmlslt_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"histcnt_z_p_zz"_h, CPUFeatures::kSVE2},
{"histseg_z_zz"_h, CPUFeatures::kSVE2},
{"ldnt1b_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
{"ldnt1b_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
{"ldnt1d_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
{"ldnt1h_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
{"ldnt1h_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
{"ldnt1sb_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
{"ldnt1sb_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
{"ldnt1sh_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
{"ldnt1sh_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
{"ldnt1sw_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
{"ldnt1w_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
{"ldnt1w_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
{"match_p_p_zz"_h, CPUFeatures::kSVE2},
{"mla_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"mla_z_zzzi_h"_h, CPUFeatures::kSVE2},
{"mla_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"mls_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"mls_z_zzzi_h"_h, CPUFeatures::kSVE2},
{"mls_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"mul_z_zz"_h, CPUFeatures::kSVE2},
{"mul_z_zzi_d"_h, CPUFeatures::kSVE2},
{"mul_z_zzi_h"_h, CPUFeatures::kSVE2},
{"mul_z_zzi_s"_h, CPUFeatures::kSVE2},
{"nbsl_z_zzz"_h, CPUFeatures::kSVE2},
{"nmatch_p_p_zz"_h, CPUFeatures::kSVE2},
{"pmul_z_zz"_h, CPUFeatures::kSVE2},
{"pmullb_z_zz"_h, CPUFeatures::kSVE2},
{"pmullt_z_zz"_h, CPUFeatures::kSVE2},
{"raddhnb_z_zz"_h, CPUFeatures::kSVE2},
{"raddhnt_z_zz"_h, CPUFeatures::kSVE2},
{"rshrnb_z_zi"_h, CPUFeatures::kSVE2},
{"rshrnt_z_zi"_h, CPUFeatures::kSVE2},
{"rsubhnb_z_zz"_h, CPUFeatures::kSVE2},
{"rsubhnt_z_zz"_h, CPUFeatures::kSVE2},
{"saba_z_zzz"_h, CPUFeatures::kSVE2},
{"sabalb_z_zzz"_h, CPUFeatures::kSVE2},
{"sabalt_z_zzz"_h, CPUFeatures::kSVE2},
{"sabdlb_z_zz"_h, CPUFeatures::kSVE2},
{"sabdlt_z_zz"_h, CPUFeatures::kSVE2},
{"sadalp_z_p_z"_h, CPUFeatures::kSVE2},
{"saddlb_z_zz"_h, CPUFeatures::kSVE2},
{"saddlbt_z_zz"_h, CPUFeatures::kSVE2},
{"saddlt_z_zz"_h, CPUFeatures::kSVE2},
{"saddwb_z_zz"_h, CPUFeatures::kSVE2},
{"saddwt_z_zz"_h, CPUFeatures::kSVE2},
{"sbclb_z_zzz"_h, CPUFeatures::kSVE2},
{"sbclt_z_zzz"_h, CPUFeatures::kSVE2},
{"shadd_z_p_zz"_h, CPUFeatures::kSVE2},
{"shrnb_z_zi"_h, CPUFeatures::kSVE2},
{"shrnt_z_zi"_h, CPUFeatures::kSVE2},
{"shsub_z_p_zz"_h, CPUFeatures::kSVE2},
{"shsubr_z_p_zz"_h, CPUFeatures::kSVE2},
{"sli_z_zzi"_h, CPUFeatures::kSVE2},
{"smaxp_z_p_zz"_h, CPUFeatures::kSVE2},
{"sminp_z_p_zz"_h, CPUFeatures::kSVE2},
{"smlalb_z_zzz"_h, CPUFeatures::kSVE2},
{"smlalb_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"smlalb_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"smlalt_z_zzz"_h, CPUFeatures::kSVE2},
{"smlalt_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"smlalt_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"smlslb_z_zzz"_h, CPUFeatures::kSVE2},
{"smlslb_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"smlslb_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"smlslt_z_zzz"_h, CPUFeatures::kSVE2},
{"smlslt_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"smlslt_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"smulh_z_zz"_h, CPUFeatures::kSVE2},
{"smullb_z_zz"_h, CPUFeatures::kSVE2},
{"smullb_z_zzi_d"_h, CPUFeatures::kSVE2},
{"smullb_z_zzi_s"_h, CPUFeatures::kSVE2},
{"smullt_z_zz"_h, CPUFeatures::kSVE2},
{"smullt_z_zzi_d"_h, CPUFeatures::kSVE2},
{"smullt_z_zzi_s"_h, CPUFeatures::kSVE2},
{"splice_z_p_zz_con"_h, CPUFeatures::kSVE2},
{"sqabs_z_p_z"_h, CPUFeatures::kSVE2},
{"sqadd_z_p_zz"_h, CPUFeatures::kSVE2},
{"sqcadd_z_zz"_h, CPUFeatures::kSVE2},
{"sqdmlalb_z_zzz"_h, CPUFeatures::kSVE2},
{"sqdmlalb_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"sqdmlalb_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"sqdmlalbt_z_zzz"_h, CPUFeatures::kSVE2},
{"sqdmlalt_z_zzz"_h, CPUFeatures::kSVE2},
{"sqdmlalt_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"sqdmlalt_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"sqdmlslb_z_zzz"_h, CPUFeatures::kSVE2},
{"sqdmlslb_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"sqdmlslb_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"sqdmlslbt_z_zzz"_h, CPUFeatures::kSVE2},
{"sqdmlslt_z_zzz"_h, CPUFeatures::kSVE2},
{"sqdmlslt_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"sqdmlslt_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"sqdmulh_z_zz"_h, CPUFeatures::kSVE2},
{"sqdmulh_z_zzi_d"_h, CPUFeatures::kSVE2},
{"sqdmulh_z_zzi_h"_h, CPUFeatures::kSVE2},
{"sqdmulh_z_zzi_s"_h, CPUFeatures::kSVE2},
{"sqdmullb_z_zz"_h, CPUFeatures::kSVE2},
{"sqdmullb_z_zzi_d"_h, CPUFeatures::kSVE2},
{"sqdmullb_z_zzi_s"_h, CPUFeatures::kSVE2},
{"sqdmullt_z_zz"_h, CPUFeatures::kSVE2},
{"sqdmullt_z_zzi_d"_h, CPUFeatures::kSVE2},
{"sqdmullt_z_zzi_s"_h, CPUFeatures::kSVE2},
{"sqneg_z_p_z"_h, CPUFeatures::kSVE2},
{"sqrdcmlah_z_zzz"_h, CPUFeatures::kSVE2},
{"sqrdcmlah_z_zzzi_h"_h, CPUFeatures::kSVE2},
{"sqrdcmlah_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"sqrdmlah_z_zzz"_h, CPUFeatures::kSVE2},
{"sqrdmlah_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"sqrdmlah_z_zzzi_h"_h, CPUFeatures::kSVE2},
{"sqrdmlah_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"sqrdmlsh_z_zzz"_h, CPUFeatures::kSVE2},
{"sqrdmlsh_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"sqrdmlsh_z_zzzi_h"_h, CPUFeatures::kSVE2},
{"sqrdmlsh_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"sqrdmulh_z_zz"_h, CPUFeatures::kSVE2},
{"sqrdmulh_z_zzi_d"_h, CPUFeatures::kSVE2},
{"sqrdmulh_z_zzi_h"_h, CPUFeatures::kSVE2},
{"sqrdmulh_z_zzi_s"_h, CPUFeatures::kSVE2},
{"sqrshl_z_p_zz"_h, CPUFeatures::kSVE2},
{"sqrshlr_z_p_zz"_h, CPUFeatures::kSVE2},
{"sqrshrnb_z_zi"_h, CPUFeatures::kSVE2},
{"sqrshrnt_z_zi"_h, CPUFeatures::kSVE2},
{"sqrshrunb_z_zi"_h, CPUFeatures::kSVE2},
{"sqrshrunt_z_zi"_h, CPUFeatures::kSVE2},
{"sqshl_z_p_zi"_h, CPUFeatures::kSVE2},
{"sqshl_z_p_zz"_h, CPUFeatures::kSVE2},
{"sqshlr_z_p_zz"_h, CPUFeatures::kSVE2},
{"sqshlu_z_p_zi"_h, CPUFeatures::kSVE2},
{"sqshrnb_z_zi"_h, CPUFeatures::kSVE2},
{"sqshrnt_z_zi"_h, CPUFeatures::kSVE2},
{"sqshrunb_z_zi"_h, CPUFeatures::kSVE2},
{"sqshrunt_z_zi"_h, CPUFeatures::kSVE2},
{"sqsub_z_p_zz"_h, CPUFeatures::kSVE2},
{"sqsubr_z_p_zz"_h, CPUFeatures::kSVE2},
{"sqxtnb_z_zz"_h, CPUFeatures::kSVE2},
{"sqxtnt_z_zz"_h, CPUFeatures::kSVE2},
{"sqxtunb_z_zz"_h, CPUFeatures::kSVE2},
{"sqxtunt_z_zz"_h, CPUFeatures::kSVE2},
{"srhadd_z_p_zz"_h, CPUFeatures::kSVE2},
{"sri_z_zzi"_h, CPUFeatures::kSVE2},
{"srshl_z_p_zz"_h, CPUFeatures::kSVE2},
{"srshlr_z_p_zz"_h, CPUFeatures::kSVE2},
{"srshr_z_p_zi"_h, CPUFeatures::kSVE2},
{"srsra_z_zi"_h, CPUFeatures::kSVE2},
{"sshllb_z_zi"_h, CPUFeatures::kSVE2},
{"sshllt_z_zi"_h, CPUFeatures::kSVE2},
{"ssra_z_zi"_h, CPUFeatures::kSVE2},
{"ssublb_z_zz"_h, CPUFeatures::kSVE2},
{"ssublbt_z_zz"_h, CPUFeatures::kSVE2},
{"ssublt_z_zz"_h, CPUFeatures::kSVE2},
{"ssubltb_z_zz"_h, CPUFeatures::kSVE2},
{"ssubwb_z_zz"_h, CPUFeatures::kSVE2},
{"ssubwt_z_zz"_h, CPUFeatures::kSVE2},
{"stnt1b_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
{"stnt1b_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
{"stnt1d_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
{"stnt1h_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
{"stnt1h_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
{"stnt1w_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
{"stnt1w_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
{"subhnb_z_zz"_h, CPUFeatures::kSVE2},
{"subhnt_z_zz"_h, CPUFeatures::kSVE2},
{"suqadd_z_p_zz"_h, CPUFeatures::kSVE2},
{"tbl_z_zz_2"_h, CPUFeatures::kSVE2},
{"tbx_z_zz"_h, CPUFeatures::kSVE2},
{"uaba_z_zzz"_h, CPUFeatures::kSVE2},
{"uabalb_z_zzz"_h, CPUFeatures::kSVE2},
{"uabalt_z_zzz"_h, CPUFeatures::kSVE2},
{"uabdlb_z_zz"_h, CPUFeatures::kSVE2},
{"uabdlt_z_zz"_h, CPUFeatures::kSVE2},
{"uadalp_z_p_z"_h, CPUFeatures::kSVE2},
{"uaddlb_z_zz"_h, CPUFeatures::kSVE2},
{"uaddlt_z_zz"_h, CPUFeatures::kSVE2},
{"uaddwb_z_zz"_h, CPUFeatures::kSVE2},
{"uaddwt_z_zz"_h, CPUFeatures::kSVE2},
{"uhadd_z_p_zz"_h, CPUFeatures::kSVE2},
{"uhsub_z_p_zz"_h, CPUFeatures::kSVE2},
{"uhsubr_z_p_zz"_h, CPUFeatures::kSVE2},
{"umaxp_z_p_zz"_h, CPUFeatures::kSVE2},
{"uminp_z_p_zz"_h, CPUFeatures::kSVE2},
{"umlalb_z_zzz"_h, CPUFeatures::kSVE2},
{"umlalb_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"umlalb_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"umlalt_z_zzz"_h, CPUFeatures::kSVE2},
{"umlalt_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"umlalt_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"umlslb_z_zzz"_h, CPUFeatures::kSVE2},
{"umlslb_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"umlslb_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"umlslt_z_zzz"_h, CPUFeatures::kSVE2},
{"umlslt_z_zzzi_d"_h, CPUFeatures::kSVE2},
{"umlslt_z_zzzi_s"_h, CPUFeatures::kSVE2},
{"umulh_z_zz"_h, CPUFeatures::kSVE2},
{"umullb_z_zz"_h, CPUFeatures::kSVE2},
{"umullb_z_zzi_d"_h, CPUFeatures::kSVE2},
{"umullb_z_zzi_s"_h, CPUFeatures::kSVE2},
{"umullt_z_zz"_h, CPUFeatures::kSVE2},
{"umullt_z_zzi_d"_h, CPUFeatures::kSVE2},
{"umullt_z_zzi_s"_h, CPUFeatures::kSVE2},
{"uqadd_z_p_zz"_h, CPUFeatures::kSVE2},
{"uqrshl_z_p_zz"_h, CPUFeatures::kSVE2},
{"uqrshlr_z_p_zz"_h, CPUFeatures::kSVE2},
{"uqrshrnb_z_zi"_h, CPUFeatures::kSVE2},
{"uqrshrnt_z_zi"_h, CPUFeatures::kSVE2},
{"uqshl_z_p_zi"_h, CPUFeatures::kSVE2},
{"uqshl_z_p_zz"_h, CPUFeatures::kSVE2},
{"uqshlr_z_p_zz"_h, CPUFeatures::kSVE2},
{"uqshrnb_z_zi"_h, CPUFeatures::kSVE2},
{"uqshrnt_z_zi"_h, CPUFeatures::kSVE2},
{"uqsub_z_p_zz"_h, CPUFeatures::kSVE2},
{"uqsubr_z_p_zz"_h, CPUFeatures::kSVE2},
{"uqxtnb_z_zz"_h, CPUFeatures::kSVE2},
{"uqxtnt_z_zz"_h, CPUFeatures::kSVE2},
{"urecpe_z_p_z"_h, CPUFeatures::kSVE2},
{"urhadd_z_p_zz"_h, CPUFeatures::kSVE2},
{"urshl_z_p_zz"_h, CPUFeatures::kSVE2},
{"urshlr_z_p_zz"_h, CPUFeatures::kSVE2},
{"urshr_z_p_zi"_h, CPUFeatures::kSVE2},
{"ursqrte_z_p_z"_h, CPUFeatures::kSVE2},
{"ursra_z_zi"_h, CPUFeatures::kSVE2},
{"ushllb_z_zi"_h, CPUFeatures::kSVE2},
{"ushllt_z_zi"_h, CPUFeatures::kSVE2},
{"usqadd_z_p_zz"_h, CPUFeatures::kSVE2},
{"usra_z_zi"_h, CPUFeatures::kSVE2},
{"usublb_z_zz"_h, CPUFeatures::kSVE2},
{"usublt_z_zz"_h, CPUFeatures::kSVE2},
{"usubwb_z_zz"_h, CPUFeatures::kSVE2},
{"usubwt_z_zz"_h, CPUFeatures::kSVE2},
{"whilege_p_p_rr"_h, CPUFeatures::kSVE2},
{"whilegt_p_p_rr"_h, CPUFeatures::kSVE2},
{"whilehi_p_p_rr"_h, CPUFeatures::kSVE2},
{"whilehs_p_p_rr"_h, CPUFeatures::kSVE2},
{"whilerw_p_rr"_h, CPUFeatures::kSVE2},
{"whilewr_p_rr"_h, CPUFeatures::kSVE2},
{"xar_z_zzi"_h, CPUFeatures::kSVE2},
{"smmla_z_zzz"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
{"ummla_z_zzz"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
{"usmmla_z_zzz"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
{"fmmla_z_zzz_s"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF32MM)},
{"fmmla_z_zzz_d"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
{"smmla_asimdsame2_g"_h,
CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kI8MM)},
{"ummla_asimdsame2_g"_h,
CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kI8MM)},
{"usmmla_asimdsame2_g"_h,
CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kI8MM)},
{"ld1row_z_p_bi_u32"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
{"ld1row_z_p_br_contiguous"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
{"ld1rod_z_p_bi_u64"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
{"ld1rod_z_p_br_contiguous"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
{"ld1rob_z_p_bi_u8"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
{"ld1rob_z_p_br_contiguous"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
{"ld1roh_z_p_bi_u16"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
{"ld1roh_z_p_br_contiguous"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
{"usdot_asimdsame2_d"_h,
CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kI8MM)},
{"sudot_asimdelem_d"_h,
CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kI8MM)},
{"usdot_asimdelem_d"_h,
CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kI8MM)},
{"usdot_z_zzz_s"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
{"usdot_z_zzzi_s"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
{"sudot_z_zzzi_s"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
{"addg_64_addsub_immtags"_h, CPUFeatures::kMTE},
{"gmi_64g_dp_2src"_h, CPUFeatures::kMTE},
{"irg_64i_dp_2src"_h, CPUFeatures::kMTE},
{"ldg_64loffset_ldsttags"_h, CPUFeatures::kMTE},
{"st2g_64soffset_ldsttags"_h, CPUFeatures::kMTE},
{"st2g_64spost_ldsttags"_h, CPUFeatures::kMTE},
{"st2g_64spre_ldsttags"_h, CPUFeatures::kMTE},
{"stgp_64_ldstpair_off"_h, CPUFeatures::kMTE},
{"stgp_64_ldstpair_post"_h, CPUFeatures::kMTE},
{"stgp_64_ldstpair_pre"_h, CPUFeatures::kMTE},
{"stg_64soffset_ldsttags"_h, CPUFeatures::kMTE},
{"stg_64spost_ldsttags"_h, CPUFeatures::kMTE},
{"stg_64spre_ldsttags"_h, CPUFeatures::kMTE},
{"stz2g_64soffset_ldsttags"_h, CPUFeatures::kMTE},
{"stz2g_64spost_ldsttags"_h, CPUFeatures::kMTE},
{"stz2g_64spre_ldsttags"_h, CPUFeatures::kMTE},
{"stzg_64soffset_ldsttags"_h, CPUFeatures::kMTE},
{"stzg_64spost_ldsttags"_h, CPUFeatures::kMTE},
{"stzg_64spre_ldsttags"_h, CPUFeatures::kMTE},
{"subg_64_addsub_immtags"_h, CPUFeatures::kMTE},
{"subps_64s_dp_2src"_h, CPUFeatures::kMTE},
{"subp_64s_dp_2src"_h, CPUFeatures::kMTE},
{"cpyen_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyern_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyewn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpye_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyfen_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyfern_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyfewn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyfe_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyfmn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyfmrn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyfmwn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyfm_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyfpn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyfprn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyfpwn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyfp_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpymn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpymrn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpymwn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpym_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpypn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyprn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpypwn_cpy_memcms"_h, CPUFeatures::kMOPS},
{"cpyp_cpy_memcms"_h, CPUFeatures::kMOPS},
{"seten_set_memcms"_h, CPUFeatures::kMOPS},
{"sete_set_memcms"_h, CPUFeatures::kMOPS},
{"setgen_set_memcms"_h,
CPUFeatures(CPUFeatures::kMOPS, CPUFeatures::kMTE)},
{"setge_set_memcms"_h,
CPUFeatures(CPUFeatures::kMOPS, CPUFeatures::kMTE)},
{"setgmn_set_memcms"_h,
CPUFeatures(CPUFeatures::kMOPS, CPUFeatures::kMTE)},
{"setgm_set_memcms"_h,
CPUFeatures(CPUFeatures::kMOPS, CPUFeatures::kMTE)},
{"setgpn_set_memcms"_h,
CPUFeatures(CPUFeatures::kMOPS, CPUFeatures::kMTE)},
{"setgp_set_memcms"_h,
CPUFeatures(CPUFeatures::kMOPS, CPUFeatures::kMTE)},
{"setmn_set_memcms"_h, CPUFeatures::kMOPS},
{"setm_set_memcms"_h, CPUFeatures::kMOPS},
{"setpn_set_memcms"_h, CPUFeatures::kMOPS},
{"setp_set_memcms"_h, CPUFeatures::kMOPS},
{"abs_32_dp_1src"_h, CPUFeatures::kCSSC},
{"abs_64_dp_1src"_h, CPUFeatures::kCSSC},
{"cnt_32_dp_1src"_h, CPUFeatures::kCSSC},
{"cnt_64_dp_1src"_h, CPUFeatures::kCSSC},
{"ctz_32_dp_1src"_h, CPUFeatures::kCSSC},
{"ctz_64_dp_1src"_h, CPUFeatures::kCSSC},
{"smax_32_dp_2src"_h, CPUFeatures::kCSSC},
{"smax_64_dp_2src"_h, CPUFeatures::kCSSC},
{"smin_32_dp_2src"_h, CPUFeatures::kCSSC},
{"smin_64_dp_2src"_h, CPUFeatures::kCSSC},
{"umax_32_dp_2src"_h, CPUFeatures::kCSSC},
{"umax_64_dp_2src"_h, CPUFeatures::kCSSC},
{"umin_32_dp_2src"_h, CPUFeatures::kCSSC},
{"umin_64_dp_2src"_h, CPUFeatures::kCSSC},
{"smax_32_minmax_imm"_h, CPUFeatures::kCSSC},
{"smax_64_minmax_imm"_h, CPUFeatures::kCSSC},
{"smin_32_minmax_imm"_h, CPUFeatures::kCSSC},
{"smin_64_minmax_imm"_h, CPUFeatures::kCSSC},
{"umax_32u_minmax_imm"_h, CPUFeatures::kCSSC},
{"umax_64u_minmax_imm"_h, CPUFeatures::kCSSC},
{"umin_32u_minmax_imm"_h, CPUFeatures::kCSSC},
{"umin_64u_minmax_imm"_h, CPUFeatures::kCSSC},
};
if (features.count(form_hash_) > 0) {
scope.Record(features[form_hash_]);
}
} else {
(it->second)(this, instr);
}
}
} // namespace aarch64
} // namespace vixl