System: Basic timings for GPU scanout
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@ -24,6 +24,8 @@ bool Core::Initialize(Bus* bus)
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void Core::Reset()
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{
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m_slice_ticks = std::numeric_limits<decltype(m_slice_ticks)>::max();
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m_regs = {};
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m_cop0_regs.BPC = 0;
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@ -40,6 +42,7 @@ void Core::Reset()
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bool Core::DoState(StateWrapper& sw)
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{
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sw.Do(&m_slice_ticks);
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sw.DoArray(m_regs.r, countof(m_regs.r));
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sw.Do(&m_regs.pc);
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sw.Do(&m_regs.hi);
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@ -269,28 +272,38 @@ void Core::DisassembleAndPrint(u32 addr)
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PrintInstruction(bits, addr);
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}
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void Core::Execute()
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TickCount Core::Execute()
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{
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// now executing the instruction we previously fetched
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const Instruction inst = m_next_instruction;
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m_current_instruction_pc = m_regs.pc;
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TickCount executed_ticks = 0;
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while (executed_ticks < m_slice_ticks)
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{
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executed_ticks++;
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// fetch the next instruction
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if (!FetchInstruction())
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return;
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// now executing the instruction we previously fetched
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const Instruction inst = m_next_instruction;
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m_current_instruction_pc = m_regs.pc;
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// handle branch delays - we are now in a delay slot if we just branched
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m_in_branch_delay_slot = m_branched;
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m_branched = false;
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// fetch the next instruction
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if (!FetchInstruction())
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continue;
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// execute the instruction we previously fetched
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ExecuteInstruction(inst);
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// handle branch delays - we are now in a delay slot if we just branched
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m_in_branch_delay_slot = m_branched;
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m_branched = false;
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// next load delay
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m_load_delay_reg = m_next_load_delay_reg;
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m_next_load_delay_reg = Reg::count;
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m_load_delay_old_value = m_next_load_delay_old_value;
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m_next_load_delay_old_value = 0;
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// execute the instruction we previously fetched
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ExecuteInstruction(inst);
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// next load delay
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m_load_delay_reg = m_next_load_delay_reg;
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m_next_load_delay_reg = Reg::count;
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m_load_delay_old_value = m_next_load_delay_old_value;
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m_next_load_delay_old_value = 0;
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}
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// reset slice ticks, it'll be updated when the components execute
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m_slice_ticks = MAX_CPU_SLICE_SIZE;
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return executed_ticks;
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}
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bool Core::FetchInstruction()
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