System: Basic timings for GPU scanout
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@ -31,7 +31,7 @@ public:
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// gpu_hw_opengl.cpp
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static std::unique_ptr<GPU> CreateHardwareOpenGLRenderer();
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void Flush();
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void Execute(TickCount ticks);
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protected:
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static constexpr u32 VRAM_WIDTH = 1024;
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@ -113,6 +113,12 @@ protected:
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void SoftReset();
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// Sets dots per scanline
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void UpdateCRTCConfig();
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// Update ticks for this execution slice
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void UpdateSliceTicks();
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// Updates dynamic bits in GPUSTAT (ready to send VRAM/ready to receive DMA)
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void UpdateGPUSTAT();
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@ -154,7 +160,7 @@ protected:
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BitField<u32, bool, 15, 1> texture_disable;
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BitField<u32, u8, 16, 1> horizontal_resolution_2;
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BitField<u32, u8, 17, 2> horizontal_resolution_1;
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BitField<u32, u8, 19, 1> vetical_resolution;
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BitField<u32, u8, 19, 1> vertical_resolution;
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BitField<u32, bool, 20, 1> pal_mode;
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BitField<u32, bool, 21, 1> display_area_color_depth_24;
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BitField<u32, bool, 22, 1> vertical_interlace;
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@ -217,6 +223,54 @@ protected:
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s32 y;
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} m_drawing_offset = {};
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struct CRTCState
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{
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struct Regs
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{
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static constexpr u32 DISPLAY_ADDRESS_START_MASK = 0b111'11111111'11111111;
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static constexpr u32 HORIZONTAL_DISPLAY_RANGE_MASK = 0b11111111'11111111'11111111;
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static constexpr u32 VERTICAL_DISPLAY_RANGE_MASK = 0b1111'11111111'11111111;
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union
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{
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u32 display_address_start;
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BitField<u32, u32, 0, 10> X;
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BitField<u32, u32, 10, 9> Y;
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};
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union
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{
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u32 horizontal_display_range;
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BitField<u32, u32, 0, 12> X1;
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BitField<u32, u32, 12, 12> X2;
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};
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union
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{
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u32 vertical_display_range;
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BitField<u32, u32, 0, 10> Y1;
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BitField<u32, u32, 10, 10> Y2;
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};
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} regs;
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u32 horizontal_resolution;
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u32 vertical_resolution;
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TickCount dot_clock_divider;
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u32 visible_horizontal_resolution;
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u32 visible_vertical_resolution;
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TickCount ticks_per_scanline;
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TickCount visible_ticks_per_scanline;
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u32 total_scanlines_per_frame;
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TickCount fractional_ticks;
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TickCount current_tick_in_scanline;
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u32 current_scanline;
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bool in_hblank;
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bool in_vblank;
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} m_crtc_state = {};
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std::vector<u32> m_GP0_command;
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std::deque<u32> m_GPUREAD_buffer;
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};
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