78 lines
1.6 KiB
C++
78 lines
1.6 KiB
C++
#pragma once
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#include "YBaseLib/Assert.h"
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#include "bus.h"
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#include "cpu_core.h"
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namespace CPU {
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template<MemoryAccessType type, MemoryAccessSize size, bool is_instruction_fetch>
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void Core::DoMemoryAccess(VirtualMemoryAddress address, u32& value)
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{
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switch (address >> 29)
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{
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case 0x00: // KUSEG 0M-512M
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{
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if constexpr (type == MemoryAccessType::Write)
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{
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if (m_cop0_regs.sr.Isc)
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return;
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}
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if (!m_bus->DispatchAccess<type, size>(address, address & UINT32_C(0x1FFFFFFF), value))
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Panic("Bus error");
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}
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break;
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case 0x01: // KUSEG 512M-1024M
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case 0x02: // KUSEG 1024M-1536M
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case 0x03: // KUSEG 1536M-2048M
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{
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// Above 512mb raises an exception.
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Panic("Bad user access");
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}
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break;
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case 0x04: // KSEG0 - physical memory cached
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{
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if constexpr (type == MemoryAccessType::Write)
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{
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if (m_cop0_regs.sr.Isc)
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return;
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}
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if (!m_bus->DispatchAccess<type, size>(address, address & UINT32_C(0x1FFFFFFF), value))
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Panic("Bus error");
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}
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break;
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case 0x05: // KSEG1 - physical memory uncached
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{
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if (!m_bus->DispatchAccess<type, size>(address, address & UINT32_C(0x1FFFFFFF), value))
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Panic("Bus error");
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}
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break;
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case 0x06: // KSEG2
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case 0x07: // KSEG2
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{
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if (address == 0xFFFE0130)
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{
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if constexpr (type == MemoryAccessType::Read)
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value = m_cache_control;
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else
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WriteCacheControl(value);
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}
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else
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{
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Panic("KSEG2 access");
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}
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}
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break;
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default:
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UnreachableCode();
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break;
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}
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}
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} // namespace CPU
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